Abstract: A fabrication process for a resistance-switching memory cell uses metal oxide as a resistance-switching material. A metal oxide film having an initial stoichiometry is deposited on an electrode using atomic layer deposition. A changed stoichiometry is provided for a portion of the metal oxide film using a plasma reduction process, separate from the atomic layer deposition, and another electrode is formed adjacent to the changed stoichiometry portion. The film deposition and the plasma reduction can be performed in separate chambers where conditions such as temperature are optimized. The metal oxide film may be deposited on a vertical sidewall in a vertical bit line 3d memory device. Optionally, the mean free path of hydrogen ions during the plasma reduction process is adjusted to increase the uniformity of the vertical metal oxide film. The adjustment can involve factors such as RF power, pressure and a bias of the wafer.

Abstract: In some aspects, a memory cell is provided that includes a first conducting layer, a reversible resistance switching element above the first conducting layer, a second conducting layer above the reversible resistance switching element, and a liner disposed about a sidewall of the reversible resistance switching element. The reversible resistance switching element includes a first metal oxide material, and the liner includes the first metal oxide material. Numerous other aspects are provided.

Abstract: A memory cell including a first electrode, a second electrode and a first resistance-switching layer located between the first and second electrodes. The first resistance-switching layer comprises hafnium silicon oxynitride.

Abstract: A memory cell including a first electrode, a second electrode and a first resistance-switching layer located between the first and second electrodes. The first resistance-switching layer comprises hafnium silicon oxynitride.