Abstract: Described is a method for validating hardware integrity on a printed circuit board assembly includes receiving a sample image of a first PCBA, where the first PCBA includes a first PCB with a first plurality of electronic components. The method also includes receiving a baseline image for a second PCBA, where the second PCBA includes a second PCB with a second plurality of electronic components. The method also includes comparing, utilizing differential analysis, the sample image to the baseline image and identifying, based on the comparing, a first area of a first anomaly associated with the first PCBA. The method also includes displaying a composite image highlighting the first area of the first anomaly associated with the first PCBA.

Abstract: An infrared sensor positioned in a reflow oven includes a reflow oven and a first IR sensor turret suspended over a conveyor surface of the reflow oven, where a directional movement of the first IR sensor turret matches a directional movement of the conveyor surface. A method for managing the IR sensor turret positioned in a reflow oven includes locating, by a first IR sensor turret, a point of interest on a PCBA, where the PCBA is positioned on a conveyor in a reflow oven. The method further includes tracking, by the first IR sensor turret, the point of interest on the PCBA, where the PCBA is moving along the conveyor in the reflow oven. The method further includes capturing, by the first IR sensor turret, a first set of thermal data at the point of interest for a first subarea of the reflow oven.

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.

Abstract: A method of fabricating a multilayer circuit board is provided which includes forming a layer of a the multilayer circuit board with an internal clearance region having a modified voltage-to-ground clearance of conductive material adjacent to an aperture of the multilayer circuit board. The modified voltage-to-ground clearance of conductive material is based on a configuration of a connector pin to be press-fit connected within the aperture of the multilayer circuit board, and the internal clearance region is enlarged in a direction of greatest normal force outward from the aperture with insertion of the connector pin into the aperture.

Abstract: An electrical connector structure is provided including a cantilever contact with a memory metal support that provides for improved cantilever contact mating. In one embodiment, the electrical contact structure includes cantilever beam having a contact portion for engaging a pin structure and a non-contact portion that is mechanical support with the contact portion. An insulated memory metal support beam is positioned adjacent to the non-contact portion of cantilever beam, wherein the insulated memory metal support beam transitions from a first geometry to a second geometry with the application of a transition element. The first geometry of the insulated memory metal support beam provides that the insulating memory metal support beam does not engage the non-contact portion of the cantilever beams. The second geometry of the insulated memory support beam contacts the non-contact portion of the cantilever beam producing a force that supports the contact portion of the cantilever contacts.

Abstract: A first apparatus includes an electrical connector with an outer shell and an inner wafer, where the inner wafer is configured to slide into a cavity of the outer shell. The first apparatus further includes a shape-memory alloy coupled to a void in the outer shell and configured to interfere with an area on the inner wafer. A second apparatus includes an OTS connector with an outer shell and an inner wafer, where the inner wafer is configured to slide into a cavity of the outer shell. The second apparatus further includes a plurality of SMT leads of the inner wafer configured to mount onto a plurality of landing pads on a PCBA. The second apparatus includes a shape-memory alloy coupled to a void in the outer shell and configured to interfere with the inner wafer preventing movement of the inner wafer within the outer shell of OTS connector.

Abstract: A controlled extraction of an electronic connector from an electronic circuit board includes a press mechanism of a device positioned in spaced relation over a base fixture of the device. The base fixture receiving an electronic circuit board which includes a connector. Shafts of a removal tool of the press mechanism can be inserted into a series of openings in the connector, respectively, in response to applying a downward force to the press mechanism. A capturing element on each of the shafts can be actuated where the capturing element couples to a wall defining the opening of each of the openings. The connector can be removed from the electronic circuit board by applying an upward force to the press mechanism which removes the connector with the capturing element of the shafts coupled to the wall of the opening, and releasing the press mechanism from the base fixture.

Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.

Abstract: Aspects include a hybrid socket dynamic warp indicator for socket connector systems and methods of using the same to measure the warpage of a printed circuit board assembly. The method can include providing a printed circuit board having a plurality of pads and a socket. A warp indicator having a plurality of solder joint connections and a resistor array is electrically coupled to the printed circuit board to build a printed circuit board assembly. The printed circuit board assembly is subjected to a thermal event. A resistance across the resistor array is measured after the thermal event. A number of separations between one or more pads of the printed circuit board and one or more solder joint connections of the warp indicator is determined based on a change in the resistance. A defective warpage condition for the socket is determined based on the number of separations.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region.

Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.

Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

Abstract: An apparatus for grounding a heatsink utilizing an EMC spring press-fit pin includes a printed circuit board, a logic chip, a heatsink, and a grounding member, where the grounding member includes an integrated spring and a first terminal pin at a first end of the grounding member. The logic chip is electrically coupled to the printed circuit board and the heatsink is disposed on a top surface of the logic chip. The first terminal pin at the first end of the grounding member is disposed in a plated-through hole of the printed circuit, where the grounding member is configured to electrically couple the heatsink to the printed circuit board.