Patents by Inventor Timothy John Mullins
Timothy John Mullins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9047116Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: GrantFiled: April 24, 2008Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Patent number: 8141098Abstract: An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: GrantFiled: January 16, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Patent number: 8140833Abstract: A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured to provide improved performance based upon the current workload.Type: GrantFiled: October 7, 2005Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Richard James Eickemeyer, Timothy Hume Heil, Harold F. Kossman, Timothy John Mullins
-
Patent number: 7617499Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of at least one instruction likely to be executed by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, one or more instructions may be prefetched on behalf of that thread so that when execution of the thread is resumed, those instructions are more likely to be cached, or at least in the process of being retrieved into cache memory, thus enabling a thread to begin executing instructions more quickly than if the thread was required to fetch those instructions upon resumption of its execution.Type: GrantFiled: December 18, 2003Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Publication number: 20090125913Abstract: An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: ApplicationFiled: January 16, 2009Publication date: May 14, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Patent number: 7493621Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: GrantFiled: December 18, 2003Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Publication number: 20080275686Abstract: A technique for reducing the number of actions performed as part of a molecular modeling simulation is disclosed. For example, embodiments of the invention may be used to reduce the number of comparisons performed in a simulation of binding affinity between a first molecule (e.g., a protein receptor site) and a second molecule (e.g., a ligand). Because such a simulation is typically performed a very large number of times for even one particular first and second molecule, and is further performed for different combinations of first and second molecules, the effect of reducing the number of comparisons is leveraged and can provide a significant impact on overall simulation performance.Type: ApplicationFiled: May 1, 2007Publication date: November 6, 2008Inventors: Timothy John Mullins, Roy Glenn Musselman, Yuan-Ping Pang, Kurt Walter Pinnow, Brian Paul Wallenfelt
-
Publication number: 20080201529Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: ApplicationFiled: April 24, 2008Publication date: August 21, 2008Applicant: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Publication number: 20080201565Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: ApplicationFiled: April 24, 2008Publication date: August 21, 2008Applicant: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
-
Patent number: 7096470Abstract: A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. Each stored thread state includes predefined selection data. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, uses the stored predefined selection data for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.Type: GrantFiled: September 19, 2002Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventors: Jeffrey Douglas Brown, Harold F. Kossman, Timothy John Mullins
-
Patent number: 6965986Abstract: A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.Type: GrantFiled: September 19, 2002Date of Patent: November 15, 2005Assignee: International Business Machines CorporationInventors: Harold F. Kossman, Timothy John Mullins
-
Publication number: 20040060052Abstract: A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. Each stored thread state includes predefined selection data. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, uses the stored predefined selection data for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: Jeffrey Douglas Brown, Harold F. Kossman, Timothy John Mullins
-
Publication number: 20040059896Abstract: A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold F. Kossman, Timothy John Mullins
-
Patent number: 6324620Abstract: Method and apparatus for managing data on DASD units to improve system performance comprises monitoring portions of data on a plurality of DASD units to determine the times the data is accessed within a given time period, and characterizing accessed data portions of a DASD unit as HOT and COLD data. The DASD units are monitored to determine the number of times each unit is accessed within a time period to develop utilization factors reflective of the number of times the DASD unit is accessed during the time period. HOT and COLD data is moved between DASD units based on the utilization factors of the DASD units.Type: GrantFiled: July 23, 1998Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Patrick James Christenson, Michael Joseph Corrigan, Thomas Richard Crowley, Michael Steven Faunce, Michael James McDermott, Timothy John Mullins, Glen Warren Nelson, Russell Paul VanDuine, Bruce Marshall Walk
-
Patent number: 6049867Abstract: A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads.Type: GrantFiled: August 4, 1997Date of Patent: April 11, 2000Assignee: International Business Machines CorporationInventors: Richard James Eickemeyer, Ross Evan Johnson, Harold F. Kossman, Steven Raymond Kunkel, Timothy John Mullins, James Allen Rose