Abstract: A method and Phase Frequency Detector (PFD) circuit for implementing low phase locked loop (PLL) phase noise and low phase error, and a design structure on which the subject circuit resides are provided. The PFD circuit includes a PFD latch receiving clock and reset signals, and PFD output driver circuit providing PFD output signals. The PFD latch is set by the clock and reset by the reset signal. An AND gate coupled to the PFD latch and the PFD output driver circuit includes differential inputs and outputs and applies the reset signal to the PFD latch. The PFD latch, AND gate and PFD output driver circuit are formed by current mode logic using bipolar transistors. An active loop filter generates a tuning voltage output.

Abstract: A method and apparatus are provided for implementing enhanced detection of circuit design limitations and stresses via enhanced waveform and schematic display. A selected simulation is run, for example, a transient, an AC, or a DC simulation. Then a displayed schematic highlights problem areas using a color set selected by a circuit designer.

Abstract: The present disclosure is directed to a method for hierarchical Very Large Scale Integrated (VLSI) mask layout data interrogation. The method displays a tree diagram of the layout hierarchy and then allows the user to interrogate the mask layout shapes by using a cross probing feature.

Abstract: An analog-to-digital (A/D) converter capable of receiving a differential input for improved noise rejection and having two static resistive ladders for reducing power consumption. The resistive ladders are anti-parallel and have a high impedance, each dividing fixed voltages into a group of reference voltages. A first stage of comparators compares the positive signal of the differential input with each of the reference voltages from one of the resistive ladder, and the negative input signal with each of the reference voltages from the other resistive ladder. The outputs of the first stage of comparators are compared by a second stage of comparators to generate a group of binary outputs in parallel. An encoder converts the outputs of the second-stage comparators into a digital value. Decoupling capacitors are also provided to reduce the AC impedance of the resistive ladders.

Abstract: A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders with a positive phase voltage source connected at the top and bottom of one of the pair of series connected resistor ladders and a negative phase voltage source connected at the top and bottom of the other one of the pair of series connected resistor ladders; both the positive phase voltage source and the negative phase voltage source including a predetermined first DC voltage value. At least one additional positive phase voltage source is connected to the one of the pair of series connected resistor ladders and at least one additional negative phase voltage source is connected to the other one of the pair of series connected resistor ladders. The additional positive phase and negative phase voltage sources include a predetermined second DC voltage value.