Abstract: A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Abstract: A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.

Abstract: A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.

Abstract: Leaked memory in a computer system is detected and recovered by first detecting memory leakage within the computer system based on nonlinear and non-parametric time-series regression analysis of software telemetry data generated by one or more software process running on the computer system. If existence of memory leakage is detected, then memory that has leaked is specifically identified and recovered. This is done by halting one or more of the software processes, generating a core image file or files of the halted software process(es), and re-starting the halted process or processes without waiting for analysis of the core image file(s). Then, the core image file is evaluated to specifically identify leaked memory in the computer system based on the core image file. Finally, the identified leaked memory is recovered.

Abstract: Leaked memory in a computer system is detected and recovered by first detecting memory leakage within the computer system based on nonlinear and non-parametric time-series regression analysis of software telemetry data generated by one or more software process running on the computer system. If existence of memory leakage is detected, then memory that has leaked is specifically identified and recovered. This is done by halting one or more of the software processes, generating a core image file or files of the halted software process(es), and re-starting the halted process or processes without waiting for analysis of the core image file(s). Then, the core image file is evaluated to specifically identify leaked memory in the computer system based on the core image file. Finally, the identified leaked memory is recovered.

Abstract: Leaked memory in a computer system is detected and recovered by first detecting memory leakage within the computer system based on nonlinear and non-parametric time-series regression analysis of software telemetry data generated by one or more software process running on the computer system. If existence of memory leakage is detected, then memory that has leaked is specifically identified and recovered. This is done by halting one or more of the software processes, generating a core image file or files of the halted software process(es), and re-starting the halted process or processes without waiting for analysis of the core image file(s). Then, the core image file is evaluated to specifically identify leaked memory in the computer system based on the core image file. Finally, the identified leaked memory is recovered.