Abstract: A method and computer system formally verifies a synthesis of integrated circuit designs that include pipeline registers. A hardware description language (HDL) representation of an integrated circuit is parsed. Components and connections of the HDL representation are identified. Pipeline register components of the HDL representation are removed. The removed pipeline register components are replaced with a conductor. Pipeline register components are added between output logic gates and output registers of the HDL representation to create a new HDL representation. Formal verification of the new HDL representation is performed using a verification tool.