Patents by Inventor Timothy L. Harris
Timothy L. Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945804Abstract: Provided herein are 4-aminoisoindoline-1,3-dione compounds having the following structure: wherein R, Ring A, and n are as defined herein, compositions comprising an effective amount of a 4-aminoisoindoline-1,3-dione compound, and methods for treating or preventing disorders.Type: GrantFiled: May 12, 2022Date of Patent: April 2, 2024Assignee: Celgene CorporationInventors: Matthew D. Alexander, Soraya Carrancio, Matthew D. Correa, Virginia Heather Sharron Grant, Joshua Hansen, Roy L. Harris, Dehua Huang, Timothy S. Kercher, Antonia Lopez-Girona, Mark A. Nagy, Veronique Plantevin-Krenitsky
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Patent number: 11941429Abstract: A computer system including one or more processors and persistent, word-addressable memory implements a persistent atomic multi-word compare-and-swap operation. On entry, a list of persistent memory locations of words to be updated, respective expected current values contained the persistent memory locations and respective new values to write to the persistent memory locations are provided. The operation atomically performs the process of comparing the existing contents of the persistent memory locations to the respective current values and, should they match, updating the persistent memory locations with the new values and returning a successful status. Should any of the contents of the persistent memory locations not match a respective current value, the operation returns a failed status. The operation is performed such that the system can recover from any failure or interruption by restoring the list of persistent memory locations.Type: GrantFiled: April 7, 2022Date of Patent: March 26, 2024Assignee: Oracle International CorporationInventors: Virendra J. Marathe, Matej Pavlovic, Alex Kogan, Timothy L. Harris
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Publication number: 20240086261Abstract: A first data accessor acquires a lock associated with a critical section. The first data accessor initiates a help session associated with a first operation of the critical section. In the help session, a second data accessor (which has not acquired the first lock) performs one or more sub-operations of the first operation. The first data accessor releases the lock after at least the first operation has been completed.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Yosef Lev, Victor M. Luchangco, David Dice, Alex Kogan, Timothy L. Harris, Pantea Zardoshti
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Publication number: 20240028424Abstract: Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: David Dice, Timothy L. Harris, Alex Kogan, Yosef Lev, Mark S. Moir
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Publication number: 20240004790Abstract: Fast modern interconnects may be exploited to control when garbage collection is performed on the nodes (e.g., virtual machines, such as JVMs) of a distributed system in which the individual processes communicate with each other and in which the heap memory is not shared. A garbage collection coordination mechanism (a coordinator implemented by a dedicated process on a single node or distributed across the nodes) may obtain or receive state information from each of the nodes and apply one of multiple supported garbage collection coordination policies to reduce the impact of garbage collection pauses, dependent on that information. For example, if the information indicates that a node is about to collect, the coordinator may trigger a collection on all of the other nodes (e.g., synchronizing collection pauses for batch-mode applications where throughput is important) or may steer requests to other nodes (e.g., for interactive applications where request latencies are important).Type: ApplicationFiled: September 18, 2023Publication date: January 4, 2024Inventors: Timothy L. Harris, Martin C. Maas
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Patent number: 11861272Abstract: A system configured to implement Comprehensive Contention-Based Thread Allocation and Placement, may generate a description of a workload from multiple profiling runs and may combine this workload description with a description of the machine's hardware to model the workload's performance over alternative thread placements. For instance, the system may generate a machine description based on executing stress applications and machine performance counters monitoring various performance indicators during execution of a synthetic workload. Such a system may also generate a workload description based on profiling sessions and the performance counters. Additionally, behavior of a workload with a proposed thread placement may be modeled based on the machine description and workload description and a prediction of the workload's resource demands and/or performance may be generated.Type: GrantFiled: August 30, 2017Date of Patent: January 2, 2024Assignee: Oracle International CorporationInventors: Timothy L. Harris, Daniel J. Goodman
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Patent number: 11861416Abstract: A first data accessor acquires a lock associated with a critical section. The first data accessor initiates a help session associated with a first operation of the critical section. In the help session, a second data accessor (which has not acquired the first lock) performs one or more sub-operations of the first operation. The first data accessor releases the lock after at least the first operation has been completed.Type: GrantFiled: July 16, 2021Date of Patent: January 2, 2024Assignee: Oracle International CorporationInventors: Yosef Lev, Victor M. Luchangco, David Dice, Alex Kogan, Timothy L. Harris, Pantea Zardoshti
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Publication number: 20230418997Abstract: A system configured to implement Comprehensive Contention-Based Thread Allocation and Placement, may generate a description of a workload from multiple profiling runs and may combine this workload description with a description of the machine's hardware to model the workload's performance over alternative thread placements. For instance, the system may generate a machine description based on executing stress applications and machine performance counters monitoring various performance indicators during execution of a synthetic workload. Such a system may also generate a workload description based on profiling sessions and the performance counters. Additionally, behavior of a workload with a proposed thread placement may be modeled based on the machine description and workload description and a prediction of the workload's resource demands and/or performance may be generated.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Timothy L. Harris, Daniel J. Goodman
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Patent number: 11809917Abstract: Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted.Type: GrantFiled: December 20, 2019Date of Patent: November 7, 2023Assignee: Oracle International CorporationInventors: David Dice, Timothy L. Harris, Alex Kogan, Yosef Lev, Mark S. Moir
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Patent number: 11797438Abstract: Fast modern interconnects may be exploited to control when garbage collection is performed on the nodes (e.g., virtual machines, such as JVMs) of a distributed system in which the individual processes communicate with each other and in which the heap memory is not shared. A garbage collection coordination mechanism (a coordinator implemented by a dedicated process on a single node or distributed across the nodes) may obtain or receive state information from each of the nodes and apply one of multiple supported garbage collection coordination policies to reduce the impact of garbage collection pauses, dependent on that information. For example, if the information indicates that a node is about to collect, the coordinator may trigger a collection on all of the other nodes (e.g., synchronizing collection pauses for batch-mode applications where throughput is important) or may steer requests to other nodes (e.g., for interactive applications where request latencies are important).Type: GrantFiled: November 12, 2021Date of Patent: October 24, 2023Assignee: Oracle International CorporationInventors: Timothy L. Harris, Martin C. Maas
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Publication number: 20230214407Abstract: Adaptive data collections may include various type of data arrays, sets, bags, maps, and other data structures. A simple interface for each adaptive collection may provide access via a unified API to adaptive implementations of the collection. A single adaptive data collection may include multiple, different adaptive implementations. A system configured to implement adaptive data collections may include the ability to adaptively select between various implementations, either manually or automatically, and to map a given workload to differing hardware configurations. Additionally, hardware resource needs of different configurations may be predicted from a small number of workload measurements. Adaptive data collections may provide language interoperability, such as by leveraging runtime compilation to build adaptive data collections and to compile and optimize implementation code and user code together.Type: ApplicationFiled: February 24, 2023Publication date: July 6, 2023Inventors: Iraklis Psaroudakis, Stefan Kaestle, Daniel J. Goodman, Jean-Pierre Lozi, Matthias Grimmer, Timothy L. Harris
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Patent number: 11593398Abstract: Adaptive data collections may include various type of data arrays, sets, bags, maps, and other data structures. A simple interface for each adaptive collection may provide access via a unified API to adaptive implementations of the collection. A single adaptive data collection may include multiple, different adaptive implementations. A system configured to implement adaptive data collections may include the ability to adaptively select between various implementations, either manually or automatically, and to map a given workload to differing hardware configurations. Additionally, hardware resource needs of different configurations may be predicted from a small number of workload measurements. Adaptive data collections may provide language interoperability, such as by leveraging runtime compilation to build adaptive data collections and to compile and optimize implementation code and user code together.Type: GrantFiled: October 9, 2020Date of Patent: February 28, 2023Assignee: Oracle International CorporationInventors: Iraklis Psaroudakis, Stefan Kaestle, Daniel J. Goodman, Jean-Pierre Lozi, Matthias Grimmer, Timothy L. Harris
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Publication number: 20220229691Abstract: A computer system including one or more processors and persistent, word-addressable memory implements a persistent atomic multi-word compare-and-swap operation. On entry, a list of persistent memory locations of words to be updated, respective expected current values contained the persistent memory locations and respective new values to write to the persistent memory locations are provided. The operation atomically performs the process of comparing the existing contents of the persistent memory locations to the respective current values and, should they match, updating the persistent memory locations with the new values and returning a successful status. Should any of the contents of the persistent memory locations not match a respective current value, the operation returns a failed status. The operation is performed such that the system can recover from any failure or interruption by restoring the list of persistent memory locations.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Inventors: Virendra J. Marathe, Matej Pavlovic, Alex Kogan, Timothy L. Harris
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Publication number: 20220066927Abstract: Fast modern interconnects may be exploited to control when garbage collection is performed on the nodes (e.g., virtual machines, such as JVMs) of a distributed system in which the individual processes communicate with each other and in which the heap memory is not shared. A garbage collection coordination mechanism (a coordinator implemented by a dedicated process on a single node or distributed across the nodes) may obtain or receive state information from each of the nodes and apply one of multiple supported garbage collection coordination policies to reduce the impact of garbage collection pauses, dependent on that information. For example, if the information indicates that a node is about to collect, the coordinator may trigger a collection on all of the other nodes (e.g., synchronizing collection pauses for batch-mode applications where throughput is important) or may steer requests to other nodes (e.g., for interactive applications where request latencies are important).Type: ApplicationFiled: November 12, 2021Publication date: March 3, 2022Inventors: Timothy L. Harris, Martin C. Maas
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Patent number: 11200164Abstract: Fast modern interconnects may be exploited to control when garbage collection is performed on the nodes (e.g., virtual machines, such as JVMs) of a distributed system in which the individual processes communicate with each other and in which the heap memory is not shared. A garbage collection coordination mechanism (a coordinator implemented by a dedicated process on a single node or distributed across the nodes) may obtain or receive state information from each of the nodes and apply one of multiple supported garbage collection coordination policies to reduce the impact of garbage collection pauses, dependent on that information. For example, if the information indicates that a node is about to collect, the coordinator may trigger a collection on all of the other nodes (e.g., synchronizing collection pauses for batch-mode applications where throughput is important) or may steer requests to other nodes (e.g., for interactive applications where request latencies are important).Type: GrantFiled: April 30, 2020Date of Patent: December 14, 2021Assignee: Oracle International CorporationInventors: Timothy L. Harris, Martin C. Maas
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Publication number: 20210342202Abstract: A first data accessor acquires a lock associated with a critical section. The first data accessor initiates a help session associated with a first operation of the critical section. In the help session, a second data accessor (which has not acquired the first lock) performs one or more sub-operations of the first operation. The first data accessor releases the lock after at least the first operation has been completed.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Yosef Lev, Victor M. Luchangco, David Dice, Alex Kogan, Timothy L. Harris, Pantea Zardoshti
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Patent number: 11157321Abstract: A runtime system for distributing work between multiple threads in multi-socket shared memory machines that may support fine-grained scheduling of parallel loops. The runtime system may implement a request combining technique in which a representative thread requests work on behalf of other threads. The request combining technique may be asynchronous; a thread may execute work while waiting to obtain additional work via the request combining technique. Loops can be nested within one another, and the runtime system may provide control over the way in which hardware contexts are allocated to the loops at the different levels. An “inside out” approach may be used for nested loops in which a loop indicates how many levels are nested inside it, rather than a conventional “outside in” approach to nesting.Type: GrantFiled: September 27, 2019Date of Patent: October 26, 2021Assignee: Oracle International CorporationInventor: Timothy L. Harris
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Patent number: 11068319Abstract: A first data accessor acquires a lock associated with a critical section. The first data accessor initiates a help session associated with a first operation of the critical section. In the help session, a second data accessor (which has not acquired the first lock) performs one or more sub-operations of the first operation. The first data accessor releases the lock after at least the first operation has been completed.Type: GrantFiled: October 18, 2018Date of Patent: July 20, 2021Assignee: Oracle International CorporationInventors: Yosef Lev, Victor M. Luchangco, David Dice, Alex Kogan, Timothy L. Harris, Pantea Zardoshti
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Publication number: 20210191788Abstract: Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: David Dice, Timothy L. Harris, Alex Kogan, Yosef Lev, Mark S. Moir
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Publication number: 20210042323Abstract: Adaptive data collections may include various type of data arrays, sets, bags, maps, and other data structures. A simple interface for each adaptive collection may provide access via a unified API to adaptive implementations of the collection. A single adaptive data collection may include multiple, different adaptive implementations. A system configured to implement adaptive data collections may include the ability to adaptively select between various implementations, either manually or automatically, and to map a given workload to differing hardware configurations. Additionally, hardware resource needs of different configurations may be predicted from a small number of workload measurements. Adaptive data collections may provide language interoperability, such as by leveraging runtime compilation to build adaptive data collections and to compile and optimize implementation code and user code together.Type: ApplicationFiled: October 9, 2020Publication date: February 11, 2021Inventors: Iraklis Psaroudakis, Stefan Kaestle, Daniel J. Goodman, Jean-Pierre Lozi, Matthias Grimmer, Timothy L. Harris