Abstract: Methods, apparatuses, and systems related to a memory controller on an interface die and outside of a processor are described. Operations of the memory controller may be further facilitated by a circuit interface fabric configured to utilize separate write and read data buses within the interface die.

Abstract: After determining that a reset pulse has reached its programmed threshold voltage level, a lower voltage verify can be conducted. This can be followed by another program step to increase the programmed threshold voltage. By avoiding the need for subsequent verification after the cell has reached its desired threshold level, read disturbs may be reduced in some embodiments. In some embodiments, by using lower voltages, it is not necessary to apply higher bias voltages to de-selected cells which may result in current leakage.

Abstract: After determining that a reset pulse has reached its programmed threshold voltage level, a lower voltage verify can be conducted. This can be followed by another program step to increase the programmed threshold voltage. By avoiding the need for subsequent verification after the cell has reached its desired threshold level, read disturbs may be reduced in some embodiments. In some embodiments, by using lower voltages, it is not necessary to apply higher bias voltages to de-selected cells which may result in current leakage.