Abstract: A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce the IC, and detects when specified ICs are inconsistent while preserving critical or fragile ICs when a two DC-pass approach is used. It further correlates the set of consistent ICs thus obtained with an equivalent circuit and simultaneously provides an input for future use. This allows a user to be notified and given a measure of how bad the inconsistencies are. Detecting inconsistencies is achieved either by measuring the holding current or by measuring the voltage drift if the two DC-pass approach is used.

Abstract: A method for accurately extracting capacitance and inductance parasitics from an electrical network representing a three-dimensional wiring of an integrated circuit chip or module is described. The extraction process can be performed either prior to or after completing a detailed wiring of the chip. In the former case, the method utilizes congestion information and approximate wiring length data to estimate the probability of encountering a particular pattern and the most accurate estimated capacitance which can arrived at. In the latter case, the wiring is partitioned into three-dimensional recognizable patterns, and a database of precomputed parasitics for each pattern is queried in order to obtain highly accurate parasitics within a limited number of machine cycles. The number of patterns is assumed to be sufficiently small to be memory and time efficient and to be arrived at in real-time.