Abstract: The disclosure provides systems, methods, and compositions for a target specific nuclease and a blunting enzyme to correct frameshift mutations for genome editing and treatment of diseases. In some embodiments, the target specific nuclease and the blunting enzyme are combined with a guide RNA and/or a microhomology-mediated end joining (MMEJ) inhibitor.

Abstract: The disclosure provides systems, methods, and compositions for a target specific nuclease and a blunting enzyme to correct frameshift mutations for genome editing and treatment of diseases. In some embodiments, the target specific nuclease and the blunting enzyme are combined with a guide RNA and/or a microhomology-mediated end joining (MMEJ) inhibitor.

Abstract: The disclosure provides systems, methods, and compositions for a target specific nuclease and a blunting enzyme to correct frameshift mutations for genome editing and treatment of diseases. In some embodiments, the target specific nuclease and the blunting enzyme are combined with a guide RNA and/or a microhomology-mediated end joining (MMEJ) inhibitor.

Abstract: The present disclosure provides lethal gene pair targets for cancer treatment, along with methods and compositions for regulating their expression and activity. Gene pairs disclosed herein include tyrosine kinase genes (e.g., SRC, RON, and YES). Also provided are methods and compositions for regulating tyrosine kinase activity, including RON specific pyrazole benzamide inhibitors and methods for gene regulation.

Abstract: We have created novel engineered genetic counter designs and methods of use thereof that utilize DNA recombinases to provide modular systems, termed single invertase memory modules (SIMMs), for encoding memory in cells and cellular systems. Our designs are easily extended to compute to high numbers, by utilizing the >100 known recombinases to create subsequent modules. Flexibility in our engineered genetic counter designs is provided by daisy-chaining individual modular components, i.e., SIMMs together. These modular components of the engineered genetic counters can be combined in other network topologies to create circuits that perform, amongst other things, logic and memory. Our novel engineered genetic counter designs allow for the maintenance of memory and provide the ability to count between discrete states by expressing the recombinases between their cognate recognition sites.

Abstract: We have created novel engineered genetic counter designs and methods of use thereof that utilize DNA recombinases to provide modular systems, termed single invertase memory modules (SIMMs), for encoding memory in cells and cellular systems. Our designs are easily extended to compute to high numbers, by utilizing the >100 known recombinases to create subsequent modules. Flexibility in our engineered genetic counter designs is provided by daisy-chaining individual modular components, i.e., SIMMs together. These modular components of the engineered genetic counters can be combined in other network topologies to create circuits that perform, amongst other things, logic and memory. Our novel engineered genetic counter designs allow for the maintenance of memory and provide the ability to count between discrete states by expressing the recombinases between their cognate recognition sites.

Abstract: A low voltage CMOS output driver is adapted to generate an output voltage that stays within predefined limits at relatively low supply voltages. The output driver includes, in part, a voltage-controlled resistor, a voltage-controlled current sink, and a switching stage. A control circuit provides the voltages that are applied to the voltage-controlled resistor and the voltage-controlled current sink. The voltage applied to the voltage-controlled resistor defines the high output voltage. The voltage applied to the voltage-controlled current sink defines the low output voltage. The control circuit is a scaled replica of the output driver and is adapted to consume a current that is 1/L times the current consumed by the output driver.

Abstract: A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.

Abstract: A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.

Abstract: A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.

Abstract: A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.