Patents by Inventor Timothy M. Archer
Timothy M. Archer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8795482Abstract: Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.Type: GrantFiled: August 10, 2012Date of Patent: August 5, 2014Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Marshall R. Stowell, John S. Drewery, Richard S. Hill, Timothy M. Archer, Avishai Kepten
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Patent number: 8268154Abstract: Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.Type: GrantFiled: August 20, 2010Date of Patent: September 18, 2012Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, John S. Drewery, Richard S. Hill, Timothy M. Archer, Avishai Kepten
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Patent number: 7501339Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.Type: GrantFiled: March 23, 2006Date of Patent: March 10, 2009Assignee: Lam Research CorporationInventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
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Patent number: 7482247Abstract: Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.Type: GrantFiled: September 19, 2006Date of Patent: January 27, 2009Assignee: Novellus Systems, Inc.Inventors: George D. Papasouliotis, Raihan M. Tarafdar, Ron Rulkins, Dennis M. Hausmann, Jeff Tobin, Adrianne K. Tipton, Bunsen Nie, Wai-Fan Yau, Brian G. Lu, Timothy M. Archer, Sasson Roger Somekh
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Patent number: 7060605Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.Type: GrantFiled: February 16, 2001Date of Patent: June 13, 2006Assignee: Lam Research CorporationInventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
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Patent number: 6909190Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.Type: GrantFiled: February 16, 2001Date of Patent: June 21, 2005Assignee: Lam Research CorporationInventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
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Publication number: 20010010970Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.Type: ApplicationFiled: February 16, 2001Publication date: August 2, 2001Inventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
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Publication number: 20010009803Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.Type: ApplicationFiled: February 16, 2001Publication date: July 26, 2001Inventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer
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Patent number: 6251770Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.Type: GrantFiled: June 30, 1999Date of Patent: June 26, 2001Assignees: Lam Research Corp., Novellus Systems, Inc.Inventors: Jay E. Uglow, Nicolas J. Bright, Dave J. Hemker, Kenneth P. MacWilliams, Jeffrey C. Benzing, Timothy M. Archer