Abstract: A semiconductor component is described which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer.

Abstract: A semiconductor component which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

Abstract: A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.