Patents by Inventor Timothy M. Takeuchi

Timothy M. Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060289202
    Abstract: A flip chip package may include stacked vias in which the diameter D1 of the outermost via is less than the diameter D2 of the innermost via. The ratio D2/D1, for example, may be 1.5 to 2.
    Type: Application
    Filed: June 24, 2005
    Publication date: December 28, 2006
    Applicant: Intel Corporation
    Inventors: Timothy M. Takeuchi, Sriram Srintvasan, Sandeep B. Sanf
  • Patent number: 7098080
    Abstract: A semiconductor package substrate has top and bottom surface buildup layers disposed on a thermally conductive substrate core. A portion of the substrate core may be exposed at a top surface of the package substrate to allow a heat spreader to be thermally coupled to the substrate core. An integrated circuit may be mounted on a top surface of the package substrate, with a top surface of the integrated circuit facing down. A heat spreader may be attached to the package substrate. The heat spreader may be thermally coupled to the substrate core and to a backside surface of the integrated circuit.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventor: Timothy M. Takeuchi
  • Patent number: 7042084
    Abstract: A semiconductor package substrate has top and bottom surface buildup layers disposed on a thermally conductive substrate core. A portion of the substrate core may be exposed at a top surface of the package substrate to allow a heat spreader to be thermally coupled to the substrate core. An integrated circuit may be mounted on a top surface of the package substrate, with a top surface of the integrated circuit facing down. A heat spreader may be attached to the package substrate. The heat spreader may be thermally coupled to the substrate core and to a backside surface of the integrated circuit.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventor: Timothy M. Takeuchi
  • Publication number: 20030122242
    Abstract: A semiconductor package substrate has top and bottom surface buildup layers disposed on a thermally conductive substrate core. A portion of the substrate core may be exposed at a top surface of the package substrate to allow a heat spreader to be thermally coupled to the substrate core. An integrated circuit may be mounted on a top surface of the package substrate, with a top surface of the integrated circuit facing down. A heat spreader may be attached to the package substrate. The heat spreader may be thermally coupled to the substrate core and to a backside surface of the integrated circuit.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventor: Timothy M. Takeuchi
  • Patent number: 6441480
    Abstract: A microelectronic package comprises a substrate, a electronic chip mounted on the substrate, a thermal interface material, a spring clip, and a retention frame. The thermal interface material is located between the electronic chip and the slug and is capable of thermally coupling the electronic chip to a slug without curing. The spring clip is located between the retention frame and the slug. In the assembled microelectronic package, the retention frame caps the substrate, and the spring clip applies a constant force to the slug to ensure reliable and continuous thermal contact between the electronic chip and the slug.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: August 27, 2002
    Assignee: Intel Corporation
    Inventors: Timothy M. Takeuchi, Imran Yusuf, Johnny M. Cook, Jr.
  • Publication number: 20020079571
    Abstract: A microelectronic package comprises a substrate, a electronic chip mounted on the substrate, a thermal interface material, a spring clip, and a retention frame. The thermal interface material is located between the electronic chip and the slug and is capable of thermally coupling the electronic chip to a slug without curing. The spring clip is located between the retention frame and the slug. In the assembled microelectronic package, the retention frame caps the substrate, and the spring clip applies a constant force to the slug to ensure reliable and continuous thermal contact between the electronic chip and the slug.
    Type: Application
    Filed: August 24, 1999
    Publication date: June 27, 2002
    Inventors: TIMOTHY M. TAKEUCHI, IMRAN YUSUF, JOHNNY M. COOK JR.