Abstract: A communication system for transmitting (T1) digital communication signals between a transmit site and a receiver site includes an M:1 multiplexer, coupled to a rate 1/N convolutional encoder, which is operative to output an encoded output signal modulated in quaternary phase shift keyed (QPSK) space having a prescribed symbol rate. The receive site has a rate 1/N Viterbi decoder which is operative to decode the encoded output signal output by the rate 1/N convolutional encoder, and a 1:M demultiplexer having an input coupled to the Viterbi decoder and M plurality of outputs, and being operative to demultiplex the decoded signal from the Viterbi decoder into a plurality of M time division multiplexed digital communication signals. For any selected values for of M and N, the product of M and N is constant.

Abstract: A measure is derived of the potential alignment of radio antennas associated with wireless transceivers, that are interfaced with terrestrial communication links transporting digital communication signals between geographically spaced apart transceiver sites. At a first radio site, a received signal strength indication is derived for signals sourced from a second radio site geographically remote with respect to the first site. In addition, received signal quality is measured on signals sourced from the second site. A measure of how well a first radio antenna at the first site is aimed in the direction of a second radio at the second site is derived in accordance with the received signal strength indication and the received signal quality measurement.

Abstract: A clock recovery scheme for a digital communication receiver has a fixed fractional delay line that is driven by a fixed frequency reference clock source, to provide a plurality of respectively offset phase delayed versions of the reference clock. A phase lock loop, to which the received signal is coupled, controllably steps through the phase delayed versions of the reference clock, so as to controllably increase or decrease the effective frequency of the reference clock and thereby produce a recovered clock signal.

Abstract: A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.