Abstract: An apparatus for monitoring the health of a peripheral component of an information handling system. An aggregation logic circuit coupled to a communication path provides data communication with each of a plurality of electrical circuits disposed on the peripheral component, the aggregation logic circuit providing a feedback signal representative of the health of the peripheral component during operation of the peripheral component.

Abstract: An apparatus for monitoring the health of a peripheral component of an information handling system. An aggregation logic circuit coupled to a communication path provides data communication with each of a plurality of electrical circuits disposed on the peripheral component, the aggregation logic circuit providing a feedback signal representative of the health of the peripheral component during operation of the peripheral component.

Abstract: An apparatus for monitoring the health of a peripheral component of an information handling system. An aggregation logic circuit coupled to a communication path provides data communication with each of a plurality of electrical circuits disposed on the peripheral component, the aggregation logic circuit providing a feedback signal representative of the health of the peripheral component during operation of the peripheral component.

Abstract: An information handling system (IHS) includes a host computer with a downstream facing host computer serial communication bus port and a serial communication bus host controller, wherein the controller is configured to detect a serial communication bus device connected to the downstream facing host computer serial communication bus port, wherein the serial communication bus device has a pull-up resistor. The IHS further includes a circuit disposed between the serial communication bus host controller and the downstream facing host computer serial communication bus port, the circuit configured to disable the downstream facing host computer serial communication bus port and comprising at least one tri-state buffer.

Abstract: An information handling system may include a video controller, multiple video interfaces configured for connecting video devices to the video controller, and a video resolution management system. The video resolution management system may be configured to determine a lowest maximum video resolution capability for relevant video devices connected to the video controller via the video interfaces, and select a video resolution for use based at least on the determined lowest maximum video resolution capability. The video controller may be configured to transmit video signals to one or more video devices according to the video resolution selected by the video resolution management system.

Abstract: An information handling system (IHS) includes a host computer with a downstream facing host computer serial communication bus port and a serial communication bus host controller, wherein the controller is configured to detect a serial communication bus device connected to the downstream facing host computer serial communication bus port, wherein the serial communication bus device has a pull-up resistor. The IHS further includes a circuit disposed between the serial communication bus host controller and the downstream facing host computer serial communication bus port, the circuit configured to disable the downstream facing host computer serial communication bus port and comprising at least one tri-state buffer.

Abstract: An apparatus for monitoring the health of a peripheral component of an information handling system. An aggregation logic circuit coupled to a communication path provides data communication with each of a plurality of electrical circuits disposed on the peripheral component, the aggregation logic circuit providing a feedback signal representative of the health of the peripheral component during operation of the peripheral component.

Abstract: A method in a data processing system for identifying a circuit. In a preferred embodiment, a set of bits, with a defined chain length, are shifted into the circuit one bit at a time. The bits shifted out from the circuit are compared to the bits, from the set of bits, shifted into the circuit to determine if the circuit corresponds to a first type circuit. The comparing step is accomplished before all bits in the set of bits have been shifted into the circuit. If the circuit is not a first type circuit corresponding to the set of bits shifted into the circuit, then the shifting of bits into the circuit is discontinued and the process is repeated with a second set of bits corresponding to a second circuit type until the circuit type has been identified.