Abstract: Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel.

Abstract: Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel.

Abstract: Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel.

Abstract: Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel.

Abstract: Trunk groups being assigned logical port values, with multiple physical ports designated to form the given trunk group, thus corresponding to the logical port. This provides greater flexibility in developing trunk groups. Each trunk group delivers frames in order. Routing and balancing decisions are based on the logical port not the physical port.

Abstract: Embodiments of methods, apparatuses and/or systems for routing a flow of frame in a core-edge switch configuration are disclosed. For example, a method of routing a flow of frames may include receiving at least one frame; selecting an exit port of a switch for the at least one frame to exit based, at least in part, on balancing frame traffic in the core-edge switch configuration; and transmitting the at least one frame.

Abstract: The present invention provides a system and a method for filtering a plurality of frames sent between devices coupled to a fabric by Fibre Channel connections. Frames are reviewed against a set of individual frame filters. Each frame filter is associated with an action, and actions selected by filter matches are prioritized. Groups of devices are “zoned” together and frame filtering ensures that restrictions placed upon communications between devices within the same zone are enforced. Zone group filtering is also used to prevent devices not within the same zone from communicating. Zoning may also be used to create LUN-level zones, protocol zones, and access control zones. In addition, individual frame filters may be created that reference selected portions of frame header or frame payload fields.

Abstract: Accordingly, there is disclosed herein an augmented Fibre Channel (FC) frame format which may provide support for multiple fabric FC networks, and may improve the performance of modularly-constructed switches. In one embodiment, the augmented FC frame format is modulated on a carrier signal and the frame includes: a start-of-frame field; a supplementary header field that follows the start-of-frame field; a frame header field that follows the supplementary header field; a cyclic redundancy code (CRC) checksum field; and an end-of-frame field that follows the CRC checksum field. The supplementary header field may include a destination tag that identifies a target fabric to which the frame is directed. Alternatively, or in addition, the supplementary header field may include an egress port identifier that identifies a switch port through which the frame is to exit a switch. The supplementary header may also include flags to request special handling by the receiver.

Abstract: Embodiments of methods, apparatuses and/or systems for logical ports in trunking are disclosed. For example, a method of routing a flow of frames may include applying a correspondence between logical ports and physical ports of a switch.

Abstract: Embodiments of methods, apparatuses and/or systems for routing a flow of frame in a core-edge switch configuration are disclosed. For example, a method of routing a flow of frames may include receiving at least one frame; selecting an exit port of a switch for the at least one frame to exit based, at least in part, on balancing frame traffic in the core-edge switch configuration; and transmitting the at least one frame.

Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: A method for computing normalized minor axis distance to an ideal line for variable-width line antialiasing. The method involves performing line primitive setup by constructing a triangle from the two line vertices and a third vertex biased from a line endpoint by the line width/2. Normalized barycentric coordinates are computed for this triangle, which together can be used for primitive attribute interpolation. One of the barycentric coordinates contains the normalized minor-axis distance to the ideal line, which can be used with a slope-correct coverage table to compute coverage. Because the minor-axis distance is normalized, the coverage value is independent of line width.