Abstract: A plurality of input/output connector modules are located along a time multiplex bus. Each module has a plurality of programmable cells comprised of digital components. Each cell can be electronically programmed to receive one bit of information. These bits of information are used by each module to determine the address and input/output configuration assumed by the module. Programming data is sent via a serial input data (SID) line to the programming cells. The SID line has a plurality of delays which are located between the modules. The delays allow all of the programming cells of one module to be programmed before the next module receives the data along the SID line. The delays are created by the intrinsic resistance of the SID line and capacitors connected to the SID line which cause a delay in the programming data. The SID line is also clamped to ground out the programming signals after each cell has been programmed.