Abstract: Data communication apparatus comprises a receiver comprising message receiver circuitry to receive payload messages and sender control messages from message sender circuitry, the message receiver circuitry comprising: communication circuitry to send receiver control messages to the message sender circuitry, the receiver control messages relating to actions by the message receiver circuitry in response to payload messages or sender control messages from the message sender circuitry; in which the communication circuitry is configured to selectively associate a respective indication with at least some of the receiver control messages sent to the message sender circuitry, the indication indicating whether a given receiver control message with which the indication is associated is a first receiver control message sent by the communication circuitry to the message sender circuitry after a reset of circuitry in the receiver.

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing instructions relating to an active virtual processor in a plurality of virtual processors. Exception control circuitry receives an external exception associated with a target virtual processor in the plurality of virtual processors and when the target virtual processor is other than the active virtual processor, it issues a doorbell exception to cause a scheduling operation to schedule the target virtual processor to be the active virtual processor. Storage circuitry stores an indication of a set of masked virtual processors and the scheduling operation is adapted to disregard doorbell exceptions in respect of the set of masked virtual processors.

Abstract: An apparatus comprises an interrupt distributor to distribute virtual interrupts to one or more physical processors, each virtual interrupt to be handled by one of a plurality of virtual processors mappable to said one or more physical processors; and control circuitry to maintain virtual processor interrupt tracking information corresponding to a given virtual processor. The virtual processor interrupt tracking information includes a pending interrupt record tracking which types of virtual interrupts are pending for the given virtual processor, and separate from the pending interrupt record, a pending interrupt status indication indicating a pending interrupt status for the given virtual processor. The pending interrupt status indicates whether the number of pending virtual interrupts for the given virtual processor is zero.

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

Abstract: Virtual processors are mappable to a number of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with further interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines, based on cached virtual processor mapping information, whether to route the interrupt request to one of the subset of physical processors or to one of the further interrupt distributors. When a rejection response is received in response to an interrupt request routed to one of the further interrupt distributors, an update of the cached virtual processing mapping information is requested based on shared virtual processor mapping information, and a resent interrupt request is sent to a further interrupt distributor determined based on the shared virtual processor mapping information.

Abstract: An apparatus comprises an interrupt distributor to distribute virtual interrupts to one or more physical processors, each virtual interrupt to be handled by one of a plurality of virtual processors mappable to said one or more physical processors; and control circuitry to maintain virtual processor interrupt tracking information corresponding to a given virtual processor. The virtual processor interrupt tracking information includes a pending interrupt record tracking which types of virtual interrupts are pending for the given virtual processor, and separate from the pending interrupt record, a pending interrupt status indication indicating a pending interrupt status for the given virtual processor. The pending interrupt status indicates whether the number of pending virtual interrupts for the given virtual processor is zero.

Abstract: Virtual processors are mappable to a number of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with further interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines, based on cached virtual processor mapping information, whether to route the interrupt request to one of the subset of physical processors or to one of the further interrupt distributors. When a rejection response is received in response to an interrupt request routed to one of the further interrupt distributors, an update of the cached virtual processing mapping information is requested based on shared virtual processor mapping information, and a resent interrupt request is sent to a further interrupt distributor determined based on the shared virtual processor mapping information.

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing instructions relating to an active virtual processor in a plurality of virtual processors. Exception control circuitry receives an external exception associated with a target virtual processor in the plurality of virtual processors and when the target virtual processor is other than the active virtual processor, it issues a doorbell exception to cause a scheduling operation to schedule the target virtual processor to be the active virtual processor. Storage circuitry stores an indication of a set of masked virtual processors and the scheduling operation is adapted to disregard doorbell exceptions in respect of the set of masked virtual processors.

Abstract: An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction.

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.

Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract: An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8. Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be synchronized to the receiving clock frequency. The clocks being used on either side of the clock boundary 8 may be switched and have a variable relationship therebetween. Multiple synchronization paths are provided within pointer synchronizing circuitry 32 which are used depending upon the particular relationship between the clocks on either side of the clock boundary 8. A pre-switch pointer value is held in a transition register 44 until a post-switch pointer value is available from the new synchronizing path 36 when a switch in clock mode is made which requires an increase in synchronization delay.

Abstract: An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8. Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be synchronised to the receiving clock frequency. The clocks being used on either side of the clock boundary 8 may be switched and have a variable relationship therebetween. Multiple synchronisation paths are provided within pointer synchronising circuitry 32 which are used depending upon the particular relationship between the clocks on either side of the clock boundary 8. A pre-switch pointer value is held in a transition register 44 until a post-switch pointer value is available from the new synchronising path 36 when a switch in clock mode is made which requires an increase in synchronisation delay.