Abstract: A method executed by a User Equipment (UE) operating in a Frame-Based Equipment (FBE) mode is provided. The method includes the following steps: determining a starting time and a periodicity of a first Fixed Frame Period (FFP) of a cell on an operating channel of an unlicensed band; determining a starting time and a periodicity of a second FFP for initiating an uplink transmission to the cell; performing a Listen-Before-Talk (LBT) procedure on the operating channel of the unlicensed band; and performing the uplink transmission to the cell using a first uplink resource in the second FFP in response to the LBT procedure indicating that the operating channel of the unlicensed band is clear.

Abstract: Techniques for compensating high-speed digital-to-analog converters (DACs) for static mismatch are described. In ideal circumstances, the current sources of a DAC are identical to each other, leading to a frequency response presenting a relatively flat noise spectrum. In the presence of mismatch, however, the response creates unwanted spurious content, which can negatively affect the DAC's dynamic range. The techniques described herein involve randomized thermometric encoders. First, the direction in which a packet contracts or expands, depending on the value to be encoded, can be randomized. Second, pairs of values in a packet (and/or pairs of values outside the packet) can be swapped with one another in a randomized fashion. Third, the decision of whether to apply randomization or not can itself be randomized. By applying one or more of the randomization techniques described herein, the negative effects of switch timing offset and errors in DC linearity can be mitigated.

Abstract: Examples pertaining to a floating frame-based channel occupancy time (COT) in a fixed frame period (FFP) in mobile communications are described. An apparatus implemented in FBE performs clear channel assessment (CCA) of a channel. The apparatus then transmits during a COT within a FFP in response to the CCA indicating the channel to be clear for transmission.

Abstract: Examples pertaining to a floating frame-based channel occupancy time (COT) in a fixed frame period (FFP) in mobile communications are described. An apparatus implemented in FBE performs clear channel assessment (CCA) of a channel. The apparatus then transmits during a COT within a FFP in response to the CCA indicating the channel to be clear for transmission.

Abstract: Examples pertaining to reserving channel by cyclic prefix (CP) extension for alignment with a symbol boundary in mobile communications are described. An apparatus extends a CP of a symbol to result in an extended symbol that aligns with a timing reference. The apparatus then transmits the extended symbol.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Techniques and examples of hybrid automatic repeat request (HARQ) buffer size design for communication systems are described. A user equipment (UE) communicates with a serving cell of a wireless network using a HARQ mechanism, with the communicating involving: (a) determining, by the processor, a respective size of each buffer of a plurality of buffers corresponding to a plurality of HARQ processes on a per-HARQ process basis; and (b) storing, by the processor, respective information in each buffer of the plurality of buffers for a corresponding HARQ process among the plurality of HARQ processes.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Examples pertaining to a floating frame-based channel occupancy time (COT) in a fixed frame period (FFP) in mobile communications are described. An apparatus implemented in FBE performs clear channel assessment (CCA) of a channel. The apparatus then transmits during a COT within a FFP in response to the CCA indicating the channel to be clear for transmission.

Abstract: Examples pertaining to reserving channel by cyclic prefix (CP) extension for alignment with a symbol boundary in mobile communications are described. An apparatus extends a CP of a symbol to result in an extended symbol that aligns with a timing reference. The apparatus then transmits the extended symbol.

Abstract: Examples pertaining to switching between load-based mode and frame-based mode when operating in unlicensed band in mobile communications are described. An apparatus implemented in a user equipment (UE) establishes wireless communication with a network in an unlicensed band. The apparatus determines to switch between a load-based equipment (LBE) mode and a frame-based equipment (FBE) mode. The apparatus then switches between the LBE mode and the FBE mode in response to the determining.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.