Patents by Inventor Timothy Phua

Timothy Phua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8034670
    Abstract: A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 11, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Timothy Phua, Bangun Indajang, Dong Kyun Sohn
  • Publication number: 20100230744
    Abstract: A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 16, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Timothy Phua, Bangun Indajang, Dong Kyun Sohn
  • Patent number: 7528445
    Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: May 5, 2009
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Timothy Phua, Kheng Chok Tee, Liang Choo Hsia
  • Publication number: 20060180848
    Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.
    Type: Application
    Filed: April 26, 2006
    Publication date: August 17, 2006
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Timothy Phua, Kheng Chok Tee, Liang Choo Hsia
  • Patent number: 7056799
    Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: June 6, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Timothy Phua, Kheng Chok Tee, Liang Choo Hsia
  • Publication number: 20060008973
    Abstract: A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLLD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process.
    Type: Application
    Filed: July 7, 2004
    Publication date: January 12, 2006
    Inventors: Timothy Phua, Kheng Tee, Liang Hsia
  • Publication number: 20050227423
    Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 13, 2005
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Timothy Phua, Kheng Tee, Liang Hsia