Abstract: A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending.

Abstract: In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned.

Abstract: A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.