Abstract: The present invention relates to a binary translator for directly translating binary instructions written for a legacy processor to executable binary instructions for a native processor. In accordance with an important aspect of the invention the binary translator is configured as a reconfigurable translator, which enables the binary translator to be used with different legacy processors and/or operating systems and native processors. The binary translators also optimize to take advantage of more efficient native processor instructions and allows portions of the legacy binary code to be disabled and/or new native instructions to be added to the application program without modification of the legacy binary code.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: The present invention relates to a binary translator for directly translating binary instructions written for a legacy processor to executable binary instructions for a native processor. In accordance with an important aspect of the invention the binary translator is configured as a reconfigurable translator, which enables the binary translator to be used with different legacy processors and/or operating systems and native processors. The binary translators also optimize to take advantage of more efficient native processor instructions and allows portions of the legacy binary code to be disabled and/or new native instructions to be added to the application program without modification of the legacy binary code.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: A method and apparatus for emulating instructions of a microprocessor (“legacy instructions”) with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of “thunk” objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.

Abstract: A system and method for implementing the paging and protection attributes, such as block protection and access lock and key functions promulgated in MIL-STD-1750A. The present invention takes advantage of the PowerPC microprocessor architecture to implement the paging and protection attributes required by MIL-STD-1750A in hardware. Since the paging and the protection attributes are implemented in hardware, the system performance is greatly improved.

Abstract: A method and apparatus for emulating instructions of one microprocessor ("legacy instructions") with instructions of another microprocessor with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, the legacy instructions are translated into direct vectors to software routines for each legacy instruction. Rather than fetching the legacy instruction and interpreting the instruction in software, the emulation system and method in accordance with the present invention fetches the direct vectors to the software routines which emulate the legacy instructions. The legacy instructions can either be translated by way of software when the legacy memory is loaded or modified, or by way of hardware when legacy memory is accessed. By fetching the direct vectors, the need for software-based look-up tables for interpreting the legacy instructions is obviated.