Abstract: A sense amplifier has a differential pair with two inputs and two outputs. The differential pair inputs can receive two analog input signals. The differential pair outputs are coupled with inputs of an amplifier with positive feedback, whose outputs are coupled with the sense amplifier outputs. Based on a clock signal, a first switch is configured for short circuiting an output signal on the sense amplifier output terminals. A second switch is configured for short circuiting a differential pair output signal. Third and fourth switches may short circuit the differential pair outputs to the supply voltage rail or the ground reference rail. The switches may include transistors, or transmission gates. The amplifier with positive feedback may include two cross-coupled inverters.

Abstract: A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations. The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

Abstract: A comparator circuit has a sense amplifier with a differential pair, a voltage excursion limiter, and a switch. The differential pair receives two analog input signals. Its differential outputs operate at a common mode voltage approximately half the supply voltage. The voltage limiter is coupled with one of the differential pair outputs. A capacitor may store comparison results. The switch energizes the differential pair and the voltage excursion limiter during a first phase of a clock, and de-energizes them during a second phase of the clock. During this phase, the comparator may provide the stored comparison result to an amplifier with positive feedback.

Abstract: A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations. The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

Abstract: A comparator circuit has a sense amplifier with a differential pair, a voltage excursion limiter, and a switch. The differential pair receives two analog input signals. Its differential outputs operate at a common mode voltage approximately half the supply voltage. The voltage limiter is coupled with one of the differential pair outputs. A capacitor may store comparison results. The switch energizes the differential pair and the voltage excursion limiter during a first phase of a clock, and de-energizes them during a second phase of the clock. During this phase, the comparator may provide the stored comparison result to an amplifier with positive feedback.