Abstract: In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post.

Abstract: Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the substrate to form an aperture (210) over a desired portion of the substrate near its outer edge. A buffer material (214), selected to impede mobile charge ingress, is implanted (310) through the aperture into the insulator layer (304) of the substrate to form a buffer structure (312).

Abstract: A method of testing integrated circuits for the effect of NBTI degradation. A static DC stress voltage is applied to the voltage supply input of the circuit. This circuit is held at this voltage for a given stress period. The application of the DC voltage is equivalent to applying a negative gate bias, and isolates the effects of NBTI degradation from CHC (channel hot carrier) degradation or other degradation that occurs when the circuit has a clocked input.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the device. The device fabrication is then completed.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the deivce. The device fabrication is then completed.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the deivce. The device fabrication is then completed.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.