Abstract: A two-stage high-power RF limiter circuit for an RF signal receiver incorporates a heavy limiting stage to limit high energy pulses of a received RF signal to a desired power threshold over a sustained time period, while a light limiting stage reacts quickly to high energy pulses to reduce spike leakage associated with the slower reaction time of the heavy limiting stage. Both heavy and light limiting stages incorporate PIN diodes biased to a voltage just below the desired power threshold (the light limiter biased to a slightly higher voltage than the heavy limiter) so the PIN diodes do not activate until power levels are high enough to warrant limiting. The holdoff voltage across the PIN diodes is maintained by Zener diodes biased to a voltage corresponding to the power threshold, allowing the PIN diodes to self-bias once the power threshold is reached.