Abstract: A pressure vessel includes a pump having a passage that extends between an inlet and an outlet. A duct at the pump outlet includes at least one dimension that is adjustable to facilitate forming a dynamic seal that limits backflow of gas through the passage.

Abstract: An apparatus that promotes the flow of materials has a body having an inner shape for holding the materials, a wall having a shape that approximates a portion of the inner shape of the body, and a vibrator attached to the wall. The wall may be disposed vertically within the body close to the body's inner shape. The vibrator transfers vibrations to the wall to agitate the material and encourage material flow.

Abstract: A chain for a particulate material extrusion pump includes a plurality of links, each of the plurality of links having a link body and a link ledge, wherein each link ledge of the plurality of links at least partially overlaps the link body of an adjacent one of the plurality of links.

Abstract: A vehicle panel control system includes a vehicle panel and a handle pivotably connected to the vehicle panel. The handle is movable about a pivot point in a first direction to unlatch or move the panel. A switch is positioned to be closed when the handle is sufficiently moved in a second direction opposite the first direction, closure of the switch is operable to unlatch or move the panel. Thus, the unlatching or movement of the panel is accomplished by either of two different motions.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

Abstract: In an LSSD/LBIST scan design, AC scan test coverage is enhanced with a scan chain configuration capable of selectively inverting scan-in signals. For example, one or more XOR gates are inserted in the scan chain. The XOR gates is controlled by a control signal preferably coming from a primary input such that original scan-in signals as well as inverted scan-in signals are shifted into the scan chain. The proposed configuration significantly enhances the AC test coverage for a scan chain having adjacent SRLs feeding the same cone of logic by adding a simple logic circuit such as an XOR gate between the adjacent SRLs.

Abstract: An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC value to determine if the electrical component passed or failed the test.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.

Abstract: In an LSSD/LBIST scan design, AC scan test coverage is enhanced with a scan chain configuration capable of selectively inverting scan-in signals. For example, one or more XOR gates are inserted in the scan chain. The XOR gates is controlled by a control signal preferably coming from a primary input such that original scan-in signals as well as inverted scan-in signals are shifted into the scan chain. The proposed configuration significantly enhances the AC test coverage for a scan chain having adjacent SRLs feeding the same cone of logic by adding a simple logic circuit such as an XOR gate between the adjacent SRLs.

Abstract: An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

Abstract: The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method provide a CRC function that is used to calculate a CRC value for a portion of memory. The CRC value is compared with an expected CRC value to determine if the electrical component passed or failed the test.