Abstract: A controller embeds a volatile memory, a plurality of application circuits and an arbiter. Each of the application circuits is capable of sending a request signal to request access the volatile memory and has a unique priority. When some of the application circuits send requests in a same period, the arbiter selects application circuits with higher priority among those application circuits such that the selected application circuits are allowed to access the volatile memory. The arbiter includes a plurality of arbiter modules and a main arbiter module. Each of the arbiter modules is assigned to a unique set of application circuits in the controller such that the arbiter modules can select higher priority application circuits in the corresponding sets at the same time. The main arbiter module further selects application circuits for accessing the volatile memory according to application circuits selected by the arbiter modules.

Abstract: A controller embeds a volatile memory, a plurality of application circuits and an arbiter. Each of the application circuits is capable of sending a request signal to request access the volatile memory and has a unique priority. When some of the application circuits send requests in a same period, the arbiter selects application circuits with higher priority among those application circuits such that the selected application circuits are allowed to access the volatile memory. The arbiter includes a plurality of arbiter modules and a main arbiter module. Each of the arbiter modules is assigned to a unique set of application circuits in the controller such that the arbiter modules can select higher priority application circuits in the corresponding sets at the same time. The main arbiter module further selects application circuits for accessing the volatile memory according to application circuits selected by the arbiter modules.

Abstract: A test platform device for testing an embedded memory of a system on chip includes a first socket, a second socket and a test control circuit. The first socket is used for plugging therein the system on chip to be tested. The second socket is used for plugging therein an independent memory chip. The test control circuit is electrically connected to the first socket and the second socket, performs a comparable writing-reading operation of each of the embedded memory of the system on chip and the independent memory chip and outputting an error data when incomparable results are obtained in response to the comparable writing-reading operation of each of the embedded memory of the system on chip and the independent memory chip.