Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An apparatus for routing signals to and from at least one circuit component that has a plurality of input/output leads includes a support structure having a first side and a second side. The first side is adapted to have the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including an array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including a first array of interconnection sites, and a second array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the package substrate. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An apparatus for routing signals to and from at least one circuit component that has a plurality of input/output leads includes a support structure having a first side and a second side. The first side is adapted to have the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.

Abstract: An apparatus for routing signals to and from at least one circuit component that has a plurality of input/output leads includes a support structure having a first side and a second side. The first side is adapted to have the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.

Abstract: An apparatus for routing signals to and from at least one circuit component that has a plurality of input/output leads includes a support structure having a first side and a second side. The first side is adapted to have the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.

Abstract: A ball grid technology circuit assembly for mounting and connecting a ball grid array circuit package having a grid array of ball pads to a printed circuit board and providing enhanced connections for testing of the ball grid array circuits. The printed circuit board includes a via array of vias wherein each via extends from the upper face of the printed circuit board to a lower face of the printed circuit board and is co-located with a ball pad of the ball grid array to provide a path between the ball pad and the lower end of the via to provide electrical access to the corresponding ball pad. A probe array includes a pin array of probe pins wherein each probe pin is co-located with a via of the via array to provide electrical contact with a ball pad of the ball grid array.

Abstract: A multi-die integrated circuit (IC) assembly and method for constructing the same are disclosed. Briefly described, the IC assembly can be constructed with a semiconductor die, a layer of die-attach material, and a flip-chip die. The semiconductor die may contain circuit elements disposed across a top surface of the die. The flip-chip die may be oriented such that circuit elements are disposed across a bottom surface of the flip-chip die. The die-attach material may contact and bond the non-circuit element surfaces of the semiconductor die an the flip-chip die (i.e., the bottom surface of the semiconductor die and the top surface of the flip-chip die). This configuration permits the close arrangements of input/output circuit drivers along the entire perimeter of each of the dies. A method for constructing the multi-die IC assembly is also presented.

Abstract: A method of forming standoff spacer pedestals on a device above the substrate by supporting the electronic device with the standoff spacer pedestals during solder reflow and bonding. Generally, the method comprising the steps of adhering at least one layer of film solder resist on the substrate, and eliminating the undesired portions of dry film solder resist to form the pedestals.