Abstract: A computing system including an application processor and a direct dataflow compute-in-memory accelerator. The direct dataflow compute-in-memory accelerator executes is configured to an execute accelerator task on accelerator data to generate an accelerator task result. An accelerator driver is configured to stream the accelerator task data from the application processor to the direct dataflow compute-in-memory architecture without placing a load on the application processor. The accelerator drive can also return the accelerator task result to the application processor.

Abstract: A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions.

Abstract: A computing system can include an off-chip memory and processing unit integrated circuitry. The processing unit IC can include on-chip compute circuitry, a first on-chip memory and a second on-chip memory. The off-chip memory can be configured to store instructions and data The first on-chip memory can be configured to store reusable portions of the instructions and or data for use by the on-chip compute circuitry. The second on-chip memory configured to cache portions of instruction and data for current use by the on-chip compute circuitry.

Abstract: A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions. The control logic can also configure array data for storage memory of the MPU.

Abstract: A memory processing unit (MPU) configuration method can include mapping operations of one or more neural network models to sets of cores in a plurality of processing regions. In addition, dataflow of the one or more neural network models can be mapped to the sets of cores in the plurality of processing regions. Furthermore, configuration information can be generated based on the mapping of the operations of the one or more neural network models to the set of cores in the plurality of processing regions and the mapping of dataflow of the one or more neural network models to the sets of cores in the plurality of processing regions. The method can be implemented by generating an initial graph from a neural network model. A mapping graph can then be generated from the final graph. One or more configuration files can then be generated from the mapping graph.

Abstract: A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of compute cores. The second memory can be coupled to the plurality of processing regions. The control logic can configure data flow between compute cores of one or more of the processing regions and corresponding adjacent regions of the first memory. The control logic can also configure data flow between the second memory and the compute cores of one or more of the processing regions. The control logic can also configure data flow between compute cores within one or more respective ones of the processing regions.

Abstract: A monolithic integrated circuit (IC) including one or more compute circuitry, one or more non-volatile memory circuits, one or more communication channels and one or more communication interface. The one or more communication channels can communicatively couple the one or more compute circuitry, the one or more non-volatile memory circuits and the one or more communication interface together. The one or more communication interfaces can communicatively couple one or more circuits of the monolithic integrated circuit to one or more circuits external to the monolithic integrated circuit.

Abstract: A processing unit can include a plurality of chiplets coupled in a cascade topology by a plurality of interfaces. A set of the plurality of cascade coupled chiplets can be configured to execute a plurality of layers or blocks of layers of an artificial intelligence model. The set of cascade coupled chiplets can also be configured with parameter data of corresponding ones of the plurality of layers or blocks of layers of the artificial intelligence model.

Abstract: Provided are antibodies that bind to bacteria associated with necrotizing enterocolitis (NEC), methods of detecting the same, and methods of using the same for treating and/or preventing NEC. The antibodies that bind to bacteria associated with NEC are detected by, e.g., detecting binding of the antibody to a bacterium in a bacterial array that includes the bacteria associated with NEC.

Abstract: Techniques for computing matrix convolutions in a plurality of multiply and accumulate units including data reuse of adjacent values. The data reuse can include reading a current value of the first matrix in from memory for concurrent use by the plurality of multiply and accumulate units. The data reuse can also include reading a current value of the second matrix in from memory to a serial shift buffer coupled to the plurality of multiply and accumulate units. The data reuse can also include reading a current value of the second matrix in from memory for concurrent use by the plurality of multiply and accumulate units.

Abstract: A monolithic integrated circuit (IC) including one or more compute circuitry, one or more non-volatile memory circuits, one or more communication channels and one or more communication interface. The one or more communication channels can communicatively couple the one or more compute circuitry, the one or more non-volatile memory circuits and the one or more communication interface together. The one or more communication interfaces can communicatively couple one or more circuits of the monolithic integrated circuit to one or more circuits external to the monolithic integrated circuit.

Abstract: A computer-implemented method for an air brake system of a train with an air brake system, including: (i) determining consist data associated with the train; (ii) determining track data comprising location data and grade data; (iii) determining required train holding force based at least partially on the consist data and the track data; and (iv) determining hand brake arrangement actuation data based at least partially on the required train holding force. An improved hand brake arrangement is also disclosed.

Abstract: An apparatus and method for steering a vehicle (not shown) provides an input member or steering wheel for receiving steering inputs from a user; a steering-torque sensor mechanically coupled to the input member for sensing the torque applied to the steering wheel; a control circuit electronically coupled to the steering-torque sensor for producing a signal corresponding to the measured driver steering torque; an output actuator electronically coupled to the control circuit and road wheel for receiving the electronic signal and translating it into mechanical motion; and an output member or road wheel mechanically coupled to the output actuator for steering the vehicle (not shown).

Abstract: An apparatus and method for steering a vehicle (not shown) provides an input member or steering wheel for receiving steering inputs from a user; a steering-torque sensor mechanically coupled to the input member for sensing the torque applied to the steering wheel; a control circuit electronically coupled to the steering-torque sensor for producing a signal corresponding to the measured driver steering torque; an output actuator electronically coupled to the control circuit and road wheel for receiving the electronic signal and translating it into mechanical motion; and an output member or road wheel mechanically coupled to the output actuator for steering the vehicle (not shown).

Abstract: A steer by wire control system having a steering wheel unit responsive to a steering wheel torque command and a road wheel unit responsive to a road wheel unit command is disclosed. A master control unit may be employed to perform processing as necessary. A method for steering a vehicle including receiving a tie-rod force signal, a road wheel position signal, a vehicle speed signal, a steering wheel position signal, and a feedback torque signal. Combining these signals to generate the steering wheel torque command signal and road wheel command signal to provide the operator with tactile feedback, while road wheel command signals are sent to road wheel units to provide steering direction. An Ackerman correction unit may also used to correct the left and right road wheel positions to track about a common center.

Abstract: A closed loop steer by wire control system has three main components, a steering wheel unit, a roadwheel unit, and a master control unit. Signals generated by sensors in the steering wheel unit and roadwheel unit are passed back to the master control unit for processing. These signals include tie-rod force signals, and a steering wheel position signal. The master control unit uses these signals to calculate a steering wheel reaction torque signal which is sent back to the steering wheel unit to provide the operator with tactile feedback, while roadwheel command signals are sent to roadwheel units to provide steering direction. An Ackerman correction unit is also used to correct the left and right roadwheel positions to track about a common center.

Abstract: A steer by wire control system having a steering wheel unit responsive to a steering wheel torque command and a road wheel unit responsive to a road wheel unit command is disclosed. A master control unit may be employed to perform processing as necessary. A method for steering a vehicle including receiving a tie-rod force signal, a road wheel position signal, a vehicle speed signal, a steering wheel position signal, and a feedback torque signal. Combining these signals to generate the steering wheel torque command signal and road wheel command signal to provide the operator with tactile feedback, while road wheel command signals are sent to road wheel units to provide steering direction. An Ackerman correction unit may also used to correct the left and right road wheel positions to track about a common center.

Abstract: An electric power steering control apparatus comprising a torque sensor coupled to a vehicle steering system for measuring steering wheel torque provided by a vehicle operator, a steering angle sensor coupled to the steering system for measuring steering wheel angle, a controller, responsive to the measured steering wheel torque and a vehicle speed, providing a sum return-to-center command, and a motor responsive to the sum return-to-center command, wherein the controller determines a low speed return-to-center command responsive to the measured steering wheel torque and a first predetermined function, determines a high speed return-to-center command responsive to the measured steering wheel torque and a second predetermined function and blends the low and high speed return-to-center commands to obtain the sum return-to-center command.