Patents by Inventor Timour T. Paltashev
Timour T. Paltashev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210049729Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.Type: ApplicationFiled: May 21, 2020Publication date: February 18, 2021Inventors: Timour T. PALTASHEV, Michael MANTOR, Rex Eldon MCCRARY
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Patent number: 10664942Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.Type: GrantFiled: October 21, 2016Date of Patent: May 26, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Timour T. Paltashev, Michael Mantor, Rex Eldon McCrary
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Patent number: 10593111Abstract: A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently of all the other sequences.Type: GrantFiled: August 7, 2018Date of Patent: March 17, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Timour T. Paltashev, Boris Prokopenko, Vladimir V. Kibardin
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Patent number: 10360177Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.Type: GrantFiled: June 22, 2016Date of Patent: July 23, 2019Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
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Publication number: 20180342099Abstract: A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently of all the other sequences.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Timour T. Paltashev, Boris Prokopenko, Vladimir V. Kibardin
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Patent number: 10068372Abstract: A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently of all the other sequences.Type: GrantFiled: December 30, 2015Date of Patent: September 4, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Timour T. Paltashev, Boris Prokopenko, Vladimir V. Kibardin
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Patent number: 10062206Abstract: A parallel adaptable graphics rasterization system in which a primitive assembler includes a router to selectively route a primitive to a first rasterizer or one of a plurality of second rasterizers. The second rasterizers concurrently operate on different primitives and the primitive is selectively routed based on an area of the primitive. In some variations, a bounding box of the primitive is reduced to a predetermined number of pixels prior to providing the primitive to the one of the plurality of second rasterizers. Reducing the bounding box can include subtracting an origin of the bounding box from coordinates of points that represent the primitive.Type: GrantFiled: August 30, 2016Date of Patent: August 28, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Boris Prokopenko, Timour T. Paltashev, Vladimir V. Kibardin
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Patent number: 10062143Abstract: A method and apparatus for real time compressing randomly accessed data includes extracting a block of randomly accessed data from a memory hierarchy. One or more individual portions of the randomly accessed data are independently compressed in real time to create a lossless compressed image surface. The compressed image surface includes data of independently compressed image blocks for reading and decompressing in a random order. The method further includes storing structured information relating to the dynamically compressed randomly accessed data.Type: GrantFiled: September 12, 2016Date of Patent: August 28, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Chris Brennan, Timour T. Paltashev
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Patent number: 10032308Abstract: A shader in a graphics pipeline accesses an object that represents a portion of a model of a scene in object space and one or more far-z values that indicate a furthest distance of a previously rendered portion of one or more tiles from a viewpoint used to render the scene on a screen. The one or more tiles overlap a bounding box of the object in a plane of the screen. The shader culls the object from the graphics pipeline in response to the one or more far-z values being smaller than a near-z value that represents a closest distance of a portion of the object to the viewpoint.Type: GrantFiled: June 22, 2016Date of Patent: July 24, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Timour T. Paltashev, Chris Brennan
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Publication number: 20180114290Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.Type: ApplicationFiled: October 21, 2016Publication date: April 26, 2018Inventors: Timour T. Paltashev, Michael Mantor, Rex Eldon McCrary
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Publication number: 20180075574Abstract: A method and apparatus for real time compressing randomly accessed data includes extracting a block of randomly accessed data from a memory hierarchy. One or more individual portions of the randomly accessed data are independently compressed in real time to create a lossless compressed image surface. The compressed image surface includes data of independently compressed image blocks for reading and decompressing in a random order. The method further includes storing structured information relating to the dynamically compressed randomly accessed data.Type: ApplicationFiled: September 12, 2016Publication date: March 15, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Chris Brennan, Timour T. Paltashev
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Publication number: 20180061124Abstract: A parallel adaptable graphics rasterization system in which a primitive assembler includes a router to selectively route a primitive to a first rasterizer or one of a plurality of second rasterizers. The second rasterizers concurrently operate on different primitives and the primitive is selectively routed based on an area of the primitive. In some variations, a bounding box of the primitive is reduced to a predetermined number of pixels prior to providing the primitive to the one of the plurality of second rasterizers. Reducing the bounding box can include subtracting an origin of the bounding box from coordinates of points that represent the primitive.Type: ApplicationFiled: August 30, 2016Publication date: March 1, 2018Inventors: Boris Prokopenko, Timour T. Paltashev, Vladimir V. Kibardin
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Publication number: 20180024938Abstract: A processing system for reduction of a virtual memory page fault rate that includes a first memory to store a dataset, a second memory to store a subset of the dataset, and a processing unit. The processing unit is configured to receive a memory access request including a virtual address and determine whether the virtual address is mapped to a first physical page in the first memory and or a second physical page in the second memory. The processing unit maps a third physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to the second physical page. The processing unit also grants access to the third physical page that is mapped to the virtual address.Type: ApplicationFiled: July 21, 2016Publication date: January 25, 2018Inventors: Timour T. Paltashev, Christopher Brennan
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Publication number: 20170371393Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
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Publication number: 20170372509Abstract: A shader in a graphics pipeline accesses an object that represents a portion of a model of a scene in object space and one or more far-z values that indicate a furthest distance of a previously rendered portion of one or more tiles from a viewpoint used to render the scene on a screen. The one or more tiles overlap a bounding box of the object in a plane of the screen. The shader culls the object from the graphics pipeline in response to the one or more far-z values being smaller than a near-z value that represents a closest distance of a portion of the object to the viewpoint.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Inventors: Timour T. Paltashev, Chris Brennan
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Publication number: 20170293432Abstract: Various memory management apparatus and methods are disclosed. In one aspect, a method of memory management is provided that includes receiving a data block in a virtual space, sub-dividing the data block into plural sub-blocks of the same size, and mapping the plural sub-blocks to a physical space according to a selected memory mapping efficiency mode.Type: ApplicationFiled: April 8, 2016Publication date: October 12, 2017Inventors: David Oldcorn, Timour T. Paltashev
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Publication number: 20170193697Abstract: A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently of all the other sequences.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Applicant: Advanced Micro Devices, Inc.Inventors: Timour T. Paltashev, Boris Prokopenko, Vladimir V. Kibardin
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Patent number: 9632848Abstract: A system and method for allocating commands in processing is disclosed. The system and method includes an application running on a computer system that provides commands to be executed on one of a plurality of processors capable of executing the commands, the commands provided through an application programming interface, a device driver that buffers the streamed commands and converts the streamed commands into a format used by a GPU, and an operating system that builds a command buffer by grouping a plurality of converted commands based on an allocation for an available processor, wherein the available processor is determined in the interface between the device driver and the operating system. The available processor is one of the plurality of processors capable of executing the commands that receives the command buffer from the operating system, queues the command buffer and performs an asynchronous submission of the command buffer to the GPU, and the GPU executes the command buffer.Type: GrantFiled: December 29, 2015Date of Patent: April 25, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David Oldcorn, Timour T. Paltashev