Abstract: An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.

Abstract: An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.

Abstract: Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that includes a plurality of register frames that are serially linked. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data is shifted into the primary register frame from a memory region that may be a ROM, RAM, soft IP of a PLD, an intelligent host or tester serial data input stream. A method for adjusting a signal through a bias circuit is also provided.

Abstract: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Abstract: Circuits, methods, and apparatus for inhibiting non-monotonic output voltage behavior in an R-2R ladder digital to analog converter (DAC). Resistance values of selected resistors of the R-2R ladder are designed to compensate for finite resistances of switches and for variances within the resistances of the resistors and of the switches. The compensating resistance values dampen or eliminate the non-monotonic behavior in the DAC.