Abstract: A wireless communication system includes: an access point used the first channel or second channel to transmit the data, wherein the center frequency of the first channel is an initial frequency and the center frequency of the second channel is an target frequency; and a client terminal. When the client terminal receives the data from the first channel, the access point and the client terminal are operated by a first working frequency and second working frequency respectively. Initially, both working frequencies are located at the initial frequency. When the first channel is desired to switch to the second channel, the first working frequency is added an offset frequency. The second working frequency is adjusted and followed so as to keep up with first working frequency. By adding the offset frequency to the working frequency repeatedly, the first and second working frequencies are shifted until both of them arrive at the target frequency.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.

Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

Abstract: Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.

Abstract: A wireless communication system includes: an access point used the first channel or second channel to transmit the data, wherein the center frequency of the first channel is an initial frequency and the center frequency of the second channel is an target frequency; and a client terminal. When the client terminal receives the data from the first channel, the access point and the client terminal are operated by a first working frequency and second working frequency respectively. Initially, both working frequencies are located at the initial frequency. When the first channel is desired to switch to the second channel, the first working frequency is added an offset frequency. The second working frequency is adjusted and followed so as to keep up with first working frequency. By adding the offset frequency to the working frequency repeatedly, the first and second working frequencies are shifted until both of them arrive at the target frequency.

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.