Abstract: A method performs a lookup on a search key word, employing a trie database including multiple trie blocks that include pointers to other trie blocks. Each trie is accessible by means of a segment of the search key. A selected section of the search key word is applied to a content addressable memory. In the event of an absence of a match of the selected section with an entry in the content addressable memory, a trie search is performed on the whole search key word. In the event of a match of the selected section with an entry in the content addressable memory, a partial trie search is performed, commencing with a first segment of the search key word after the selected section that has been matched in the content addressable memory.

Abstract: An interface between a wireless node and a network node includes an encapsulator for temporarily converting data frames into Ethernet frames for the link between the two nodes and de-encapsulating the Ethernet frames before the data is processed at the network node.

Abstract: A search engine operable to search on a search key word of a given length comprises a trie database which supports a trie search on keys of the given length and a content addressable memory organized to receive a most significant section of the search key word. The search engine performs a full trie search on the whole of said search key word in the event of no match of a most significant section within the content addressable memory. In the event of a match within the content addressable memory the search engine performs a partial trie search commencing with a trie block pertaining to a first segment of the search key word after the most significant section which has already been matched.

Abstract: A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory. The cache memory may be a multiple way set associative cache memory with the system including a round robin allocator for controlling the storing of successive data items in the different ways of the set associative cache. The cache may also be a direct mapped cache having single way set-associativity so that the round robin allocator is not required. The system may also include a direct memory access (DMA) device for copying data items into the memory. The memory may be a buffer memory which is divided into a plurality of packet buffers.

Abstract: A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory

Abstract: An interface between a wireless node and a network node includes an encapsulator for temporarily converting data frames into Ethernet frames for the link between the two nodes and de-encapsulating the Ethernet frames before the data is processed at the network node