Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first contact formed over a second portion of the one or more fins, wherein the first contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first contact to the first metal line, and a second via connecting the first contact to the second metal line, wherein the second via is placed on the extended portion of the first contact.

Abstract: Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias.

Abstract: A die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

Abstract: In certain aspects of the disclosure, a die includes one or more fins, a gate formed over a first portion of the one or more fins, and a first source/drain contact formed over a second portion of the one or more fins, wherein the first source/drain contact includes an extended portion that does not overlap the one or more fins. The die also includes first and second metal lines formed from a first metal layer, wherein the first and second metal lines are spaced apart. The die further includes a first via connecting the first source/drain contact to the first metal line, and a second via connecting the first source/drain contact to the second metal line, wherein the second via lies within the extended portion of the first source/drain contact.

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract: A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

Abstract: A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract: A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

Abstract: A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.

Abstract: A die is provided having an unterminated endpoint that capacitively loads its input impedance with a capacitance from capacitor while acting as a receiving endpoint and that isolates its output impedance from the capacitance while acting as a transmitting endpoint.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but- for the equalizer.

Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but-for the equalizer.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.