Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is disposed closer to the thermal conductive plate than the drain terminal.

Abstract: A flyback converter includes a transformer, a sensing impedance, a switch and a control circuit. The sensing impedance is coupled between the transformer and an output terminal of the flyback converter. The switch is coupled to the transformer. The transformer is charged when the switch activates. The transformer is discharged when the switch deactivates. The control circuit is arranged to detect if the sensing impedance is bypassed, and further arranged to adjust an operating frequency of the switch when the sensing impedance is bypassed.

Abstract: A flyback converter includes a transformer, a sensing impedance, a switch and a control circuit. The sensing impedance is coupled between the transformer and an output terminal of the flyback converter. The switch is coupled to the transformer. The transformer is charged when the switch activates. The transformer is discharged when the switch deactivates. The control circuit is arranged to detect if the sensing impedance is bypassed, and further arranged to adjust an operating frequency of the switch when the sensing impedance is bypassed.

Abstract: A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is disposed closer to the thermal conductive plate than the drain terminal.

Abstract: A PWM controller having an oscillator, a control circuit and a two-level limiter is provided. The oscillator generates a pulse signal. The control circuit couples to the oscillator for generating a PWM signal in response to the pulse signal, wherein the PWM signal controls a power switch. The two-level limiter couples to the control circuit for generating a two-level limit signal in response to an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal, and the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition, and the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with the heavy-load condition.

Abstract: A PWM controller having an oscillator, a control circuit and a two-level limiter is provided. The oscillator generates a pulse signal. The control circuit couples to the oscillator for generating a PWM signal in response to the pulse signal, wherein the PWM signal controls a power switch. The two-level limiter couples to the control circuit for generating a two-level limit signal in response to an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal, and the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition, and the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with the heavy-load condition.