Patents by Inventor Tin-Wei Wu
Tin-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961810Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.Type: GrantFiled: June 21, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
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Patent number: 9543319Abstract: A vertical channel structure including a substrate, a plurality of stacked structures, a charge storage structure, a channel structure and a dielectric structure is provided. The stacked structures are disposed on the substrate. An opening is located between the stacked structures. The charge storage structure is disposed on a sidewall of the opening. The channel structure is disposed on the charge storage structure and on the substrate at a bottom portion of the opening. The dielectric structure includes first and second dielectric layers. The first dielectric layer is disposed on the channel structure. The second dielectric layer is disposed on the first dielectric layer and seals the opening to form a void in the dielectric structure. A top portion of the second dielectric layer is higher than a top portion of the first dielectric layer. The dielectric structure exposes an upper portion of the channel structure.Type: GrantFiled: November 19, 2015Date of Patent: January 10, 2017Assignee: MACRONIX International Co., Ltd.Inventors: Tin-Wei Wu, Chih-Hsiang Yang
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Patent number: 8471324Abstract: A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.Type: GrantFiled: September 15, 2009Date of Patent: June 25, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Tin-Wei Wu, Cheng-Ming Yih, Chih-Hsiang Yang
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Patent number: 8450180Abstract: Methods of forming a semiconductor trench and forming dual trenches and a structure for isolating devices are provided. The structure for isolating devices is disposed in a substrate having a periphery area and an array area. The structure for isolating devices includes a first isolation structure and a second isolation structure. The first isolation structure has a profile with at least three steps and is disposed in the substrate in the periphery area. The second isolation structure has a profile with at least two steps and is disposed in the substrate in the array area.Type: GrantFiled: December 30, 2010Date of Patent: May 28, 2013Assignee: MACRONIX International Co. Ltd.Inventors: Chu-Ming Ma, Tin-Wei Wu, Chih-Hsiang Yang
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Publication number: 20120168897Abstract: Methods of forming a semiconductor trench and forming dual trenches and a structure for isolating devices are provided. The structure for isolating devices is disposed in a substrate having a periphery area and an array area. The structure for isolating devices includes a first isolation structure and a second isolation structure. The first isolation structure has a profile with at least three steps and is disposed in the substrate in the periphery area. The second isolation structure has a profile with at least two steps and is disposed in the substrate in the array area.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: MACRONIX International Co., Ltd.Inventors: Chu-Ming Ma, Tin-Wei Wu, Chih-Hsiang Yang
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Publication number: 20110062507Abstract: A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Tin-Wei Wu, Cheng-Ming Yih, Chih-Hsiang Yang
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Patent number: 7061041Abstract: A memory device is provided. The memory device comprises a substrate, first isolation structures, stacked device structures, and second isolation structures. The substrate comprises a memory cell area and a periphery area having trenches therein. Each stacked device structure is disposed between two neighboring trenches over the substrate. The stacked device structure comprises a gate dielectric layer and a gate layer. The gate dielectric layer covers part of the substrate. The second isolation structures are disposed between neighboring stacked device structures. The second isolation structure comprises a liner and an isolation layer. The liner is disposed on the sidewalls of the gate dielectric layer, the surface of the trenches, and the surface of the substrate not covered by the dielectric layer. The liner over the surface of the substrate not covered by the dielectric layer has a round curve. The isolation layer covers the liner, and fills the trenches.Type: GrantFiled: October 13, 2004Date of Patent: June 13, 2006Assignee: Winbond Electronics Corp.Inventors: Tin-Wei Wu, Po-An Chen
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Publication number: 20060038219Abstract: A memory device is provided. The memory device comprises a substrate, first isolation structures, stacked device structures, and second isolation structures. The substrate comprises a memory cell area and a periphery area having trenches therein. Each stacked device structure is disposed between two neighboring trenches over the substrate. The stacked device structure comprises a gate dielectric layer and a gate layer. The gate dielectric layer covers part of the substrate. The second isolation structures are disposed between neighboring stacked device structures. The second isolation structure comprises a liner and an isolation layer. The liner is disposed on the sidewalls of the gate dielectric layer, the surface of the trenches, and the surface of the substrate not covered by the dielectric layer. The liner over the surface of the substrate not covered by the dielectric layer has a round curve. The isolation layer covers the liner, and fills the trenches.Type: ApplicationFiled: October 13, 2004Publication date: February 23, 2006Inventors: Tin-Wei Wu, Po-An Chen