Patents by Inventor Tina C. Zhong
Tina C. Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11630691Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.Type: GrantFiled: August 24, 2021Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: Robert Pawlowski, Ankit More, Jason M. Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith, Sowmya Pitchaimoorthy, Samkit Jain, Vincent Cave, Sriram Aananthakrishnan, Bharadwaj Krishnamurthy
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Publication number: 20210389984Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.Type: ApplicationFiled: August 24, 2021Publication date: December 16, 2021Inventors: Robert PAWLOWSKI, Ankit MORE, Jason M. HOWARD, Joshua B. FRYMAN, Tina C. ZHONG, Shaden SMITH, Sowmya PITCHAIMOORTHY, Samkit JAIN, Vincent CAVE, Sriram AANANTHAKRISHNAN, Bharadwaj KRISHNAMURTHY
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Patent number: 11106494Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.Type: GrantFiled: September 28, 2018Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Robert Pawlowski, Ankit More, Jason M. Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith, Sowmya Pitchaimoorthy, Samkit Jain, Vincent Cave, Sriram Aananthakrishnan, Bharadwaj Krishnamurthy
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Patent number: 10929330Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.Type: GrantFiled: June 30, 2017Date of Patent: February 23, 2021Assignee: INTEL CORPORATIONInventors: Chih-Cheh Chen, Russell J. Wunderlich, Tina C. Zhong
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Patent number: 10620966Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.Type: GrantFiled: September 28, 2017Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Tina C. Zhong, Russell J. Wunderlich, Chih-Cheh Chen, Malay Trivedi
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Publication number: 20200104164Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Robert PAWLOWSKI, Ankit MORE, Jason M. HOWARD, Joshua B. FRYMAN, Tina C. ZHONG, Shaden SMITH, Sowmya PITCHAIMOORTHY, Samkit JAIN, Vincent CAVE, Sriram AANANTHAKRISHNAN, Bharadwaj KRISHNAMURTHY
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Micro-architectural techniques to minimize companion die firmware loading times in a server platform
Patent number: 10496565Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.Type: GrantFiled: July 30, 2018Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Anand K. Enamandram, Sivakumar Radhakrishnan, Jayasekhar Tholiyil, Tina C. Zhong, Malay Trivedi -
Publication number: 20190095224Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Tina C. Zhong, Russell J. Wunderlich, Chih-Cheh Chen, Malay Trivedi
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MICRO-ARCHITECTURAL TECHNIQUES TO MINIMIZE COMPANION DIE FIRMWARE LOADING TIMES IN A SERVER PLATFORM
Publication number: 20190042514Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.Type: ApplicationFiled: July 30, 2018Publication date: February 7, 2019Inventors: Anand K. ENAMANDRAM, Sivakumar RADHAKRISHNAN, Jayasekhar THOLIYIL, Tina C. ZHONG, Malay TRIVEDI -
Publication number: 20190004989Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: INTEL CORPORATIONInventors: Chih-Cheh Chen, Russell J. Wunderlich, Tina C. Zhong
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Patent number: 8799728Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: October 25, 2013Date of Patent: August 5, 2014Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Publication number: 20140053026Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Inventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8589745Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: December 11, 2012Date of Patent: November 19, 2013Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8543776Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: October 31, 2012Date of Patent: September 24, 2013Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Publication number: 20130103987Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: ApplicationFiled: December 11, 2012Publication date: April 25, 2013Inventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Publication number: 20130054931Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: ApplicationFiled: October 31, 2012Publication date: February 28, 2013Inventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8327198Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: August 14, 2009Date of Patent: December 4, 2012Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Publication number: 20110041017Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: ApplicationFiled: August 14, 2009Publication date: February 17, 2011Inventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger