Patents by Inventor Tina L. Gardner

Tina L. Gardner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030104680
    Abstract: A process of removing metallic impurities from a polished boron-doped silicon wafer comprising forming an oxide layer on the polished wafer that is thicker than a typical native oxide layer so that the oxide layer has a greater gettering capacity than a native oxide layer gettering capacity and then annealing the wafer at a temperature of at least about 75° C. for at least about 30 seconds to decrease the concentration of the metallic impurity in the interior of the silicon wafer and increase the concentration of the metallic impurity on the polished surface of the silicon wafer and in the oxide layer. Preferably, the annealed silicon wafer is cleaned to remove the oxide layer and to remove the metallic impurity from the polished surface of the silicon wafer. By repeatedly creating an oxide layer and annealing the wafer, the wafer can be made substantially free of metallic impurities.
    Type: Application
    Filed: November 13, 2002
    Publication date: June 5, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Andrei D. Stefanescu, Leonard O. Rosik, Tina L. Gardner