Patents by Inventor Tina Y Liu

Tina Y Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141412
    Abstract: Described herein are nucleic acid detection compositions and systems comprising an internal nuclease chain reaction (NCR) for signal amplification and methods of using these NCR-containing compositions and systems.
    Type: Application
    Filed: May 18, 2021
    Publication date: May 2, 2024
    Inventors: David Savage, Patrick Hsu, Noam Prywes, Emeric J. Charles, Gavin J. Knott, John James Desmarais, Shineui Kim, Eli Dugan, Maria Lukarska, Sita S. Chandrasekaran, Nicholas C. Lammers, Tina Y. Liu, Amanda Mok, Liana Lareau, Brittney Wai-Ling Thornton
  • Publication number: 20230357761
    Abstract: Described herein are compositions and systems comprising activators of type III accessory nucleases and methods of using these compositions and systems.
    Type: Application
    Filed: September 20, 2021
    Publication date: November 9, 2023
    Inventors: Jennifer Doudna, Patrick Hsu, David Savage, Tina Y. Liu, Shrutee Jakhanwal, Noam Prywes, Gavin J. Knott, Brittney Wai-Ling Thornton, Dylan C.J. Smock, Emeric J. Charles, Shineui Kim
  • Patent number: 8698063
    Abstract: A method of reading out photocurrent. A readout integrate circuit (ROIC) is provided including an integration capacitor (Cint) having a charging electrode. The ROIC provides linear operation over a linear pixel output signal range when a voltage across Cint (Vint) is in a Vint range between Vlin1-cap and Vlin2-cap, and a non-linear operation range outside the Vint range. A reset voltage (Vrst) is applied to the charging electrode to reset Vint outside the Vint range. The photocurrent is integrated to generate integrated photocurrent during a frame including integrating from Vrst toward the Vint range to integrate background current into the non-linear operation range and integrating to a voltage within the Vint range to integrate scene current into the linear pixel output signal range. The integrated photocurrent is processed to generate a pixel output signal. The pixel output signal excludes some background current that was integrated into the non-linear operation range.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 15, 2014
    Assignee: Lockheed Martin Corporation
    Inventor: Tina Y. Liu
  • Publication number: 20120145883
    Abstract: A method of reading out photocurrent. A readout integrate circuit (ROIC) is provided including an integration capacitor (Cint) having a charging electrode. The ROIC provides linear operation over a linear pixel output signal range when a voltage across Cint (Vint) is in a Vint range between Vlin1-cap and Vlin2-cap, and a non-linear operation range outside the Vint range. A reset voltage (Vrst) is applied to the charging electrode to reset Vint outside the Vint range. The photocurrent is integrated to generate integrated photocurrent during a frame including integrating from Vrst toward the Vint range to integrate background current into the non-linear operation range and integrating to a voltage within the Vint range to integrate scene current into the linear pixel output signal range. The integrated photocurrent is processed to generate a pixel output signal. The pixel output signal excludes some background current that was integrated into the non-linear operation range.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 14, 2012
    Applicant: LOCKHEED MARTIN CORPORATION
    Inventor: Tina Y. Liu
  • Patent number: 7154548
    Abstract: An electronic imaging chip containing an array of photodiodes includes a multiplexed column buffer. The multiplexed column buffer serves a plurality of columns in the photodiode array. By multiplexing active amplifier elements, such as the differential gain amplifiers and the bus driver amplifiers, a wider area than one column width is available on the semiconductor chip for layout of the column buffer. In the disclosed embodiment, 4 columns share a common multiplexed column buffer. The area available for layout of the multiplexed column buffer is 4 times as wide as compared to that for a non-multiplexed column buffer.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: December 26, 2006
    Assignee: Valley Oak Semiconductor
    Inventor: Tina Y Liu
  • Patent number: 6950131
    Abstract: A semiconductor chip for forming an electronic image in a digital camera includes an offset canceling column buffer for use with active pixel sensors having a small electrical buffer amplifier within each pixel The active pixel sensors are arranged on a semiconductor chip with simultaneous access and reset lines. Each active pixel sensor includes an source follower current amplifier, which introduces small variations in offset voltage, causing pattern noise to be introduced into the output signal of the sensed image. A method and apparatus is disclosed for addressing an array of active pixel sensors in a sequence coordinated with a column buffer for canceling pattern noise. To cancel pattern noise, the current row N in the APS cell array is accessed and sampled. Next, the following row N+1 is accessed thereby resetting the current row. Finally, the previous row N in the APS cell array is accessed a second time and sampled.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: September 27, 2005
    Assignee: Valley Oak Semiconductor
    Inventors: William A Kleinhans, Tina Y Liu
  • Publication number: 20020100862
    Abstract: An electronic imaging chip containing an array of photodiodes includes a multiplexed column buffer. The multiplexed column buffer serves a plurality of columns in the photodiode array. By multiplexing active amplifier elements, such as the differential gain amplifiers and the bus driver amplifiers, a wider area than one column width is available on the semiconductor chip for layout of the column buffer. In the disclosed embodiment, 4 columns share a common multiplexed column buffer. The area available for layout of the multiplexed column buffer is 4 times as wide as compared to that for a non-multiplexed column buffer.
    Type: Application
    Filed: January 29, 2001
    Publication date: August 1, 2002
    Applicant: Valley Oak Semiconductor, Inc.
    Inventor: Tina Y. Liu