Patents by Inventor Ting-An Lin

Ting-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12046547
    Abstract: The present disclosure provides an electronic device including a substrate, a first pad, an insulating layer, a second pad, a conductive element and a chip. The first pad is disposed on the substrate. The insulating layer is disposed on the first pad and has a plurality of first openings. The second pad is electrically connected to the first pad through the first openings. The conductive particle is disposed on the second pad. The chip is electrically connected to the second pad through the conductive element. In a top view of the electronic device, the first openings are arranged along a long edge of the first pad, and an outline of at least one first opening has a curved shape.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: July 23, 2024
    Assignee: InnoLux Corporation
    Inventors: Mei-Chi Hsu, Yu-Chin Lin, Yu-Ting Liu
  • Patent number: 12048154
    Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: July 23, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hong-Ji Lee, Tzung-Ting Han, Lo Yueh Lin, Chih-Chin Chang, Yu-Fong Huang, Yu-Hsiang Yeh
  • Publication number: 20240243345
    Abstract: A method of forming a solid-state electrolyte powder includes the following steps. A zirconium compound layer is formed on an inner surface of a container. A precursor mixture is placed on the zirconium compound layer. The precursor mixture includes a first salt group and a second salt group. The first salt group includes zirconium source compound, lanthanum source compound, aluminum source compound, titanium source compound, tantalum source compound, or combinations thereof. The second salt group includes lithium source compound. An aerobic sintering process is performed to form the solid-state electrolyte powder.
    Type: Application
    Filed: May 23, 2023
    Publication date: July 18, 2024
    Inventors: Cheng-Ting Lin, Hong-Zheng Lai, Tseng-Lung Chang, Yu-Han Li
  • Publication number: 20240243185
    Abstract: Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.
    Type: Application
    Filed: February 17, 2023
    Publication date: July 18, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Huan Chi Ma, Kuan-Ting Lin, Ying Jie Huang, Chien-Wen Yu
  • Publication number: 20240243075
    Abstract: A chip package with heat dissipation and electromagnetic protection is provided. The chip package includes a package unit and a heat dissipation shielding layer. A top portion of the package unit is formed by grinding of an original top of the package unit using grinding technique and a level of a back surface of at least one die is at the same level with the top portion of the package unit after the grinding. The heat dissipation shielding layer is completely covering the top portion of the package unit for providing functions of heat dissipation and electromagnetic protection to the package unit.
    Type: Application
    Filed: December 21, 2023
    Publication date: July 18, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Patent number: 12040607
    Abstract: A voltage stabilizer is provided for stabilizing a gate-source voltage of a switching element, wherein a source of the switching element receives a first driving voltage. The voltage stabilizer includes a transistor and a first resistor. A base of the transistor receives a second driving voltage, a collector of the bipolar junction transistor is electrically connected to a gate of the switching element, a first terminal of the first resistor is electrically connected to the collector and the gate, a second terminal of the first resistor is electrically connected to the source of the switching element and receives the first driving voltage.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: July 16, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kuan-Ting Lee, Chen-Chieh Kao, Yu-Liang Lin, Cheng-Chia Hsiao
  • Patent number: 12040219
    Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Chung Huang, Chiung-Wen Hsu, Mei-Ju Kuo, Yu-Ting Weng, Yu-Chi Lin, Ting-Chung Wang, Chao-Cheng Chen
  • Patent number: 12038379
    Abstract: A sanitary device for the urine glucose test includes a urine container formed on an inner wall of a main body, and a measuring module with an inner space mounted at a bottom of the urine container. Within the inner space, a lens attaches to the bottom of the urine container, a rail faces a bottom surface of the lens, and a driving module moves a light unit shooting a detection beam to a measuring surface of the lens along the rail. The measuring surface contacts urine in the urine container, and reflects the detection beam out of the bottom surface into a sensor. The sensor is electrically connected to a processor. The processor determines a urine glucose level and generates a urine glucose level data instantly from an angle of incidence of the detection beam on the measuring surface and from a beam intensity signal from the sensor.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan RedEye Biomedical Inc.
    Inventors: Shuo-Ting Yan, Tsung-Jui Lin, Yu-Hsun Chen, Kuan-Wei Su
  • Publication number: 20240237326
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: October 25, 2022
    Publication date: July 11, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240231203
    Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.
    Type: Application
    Filed: October 24, 2023
    Publication date: July 11, 2024
    Applicant: Coretronic Corporation
    Inventors: Wei-Min Chien, Yen-Ting Lin, Yao-Hung Chen
  • Publication number: 20240234035
    Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.
    Type: Application
    Filed: February 18, 2024
    Publication date: July 11, 2024
    Inventors: Mao-Ying WANG, Yu-Ting LIN
  • Publication number: 20240234530
    Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.
    Type: Application
    Filed: June 6, 2023
    Publication date: July 11, 2024
    Inventors: Chun-Hsiung TSAI, Yu-Ming LIN, Kuo-Feng YU, Yu-Ting LIN, Ming-Te CHEN, Yi-Hsiu HUANG
  • Publication number: 20240237327
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: July 18, 2023
    Publication date: July 11, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240237554
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.
    Type: Application
    Filed: March 21, 2024
    Publication date: July 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
  • Publication number: 20240237551
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Publication number: 20240225264
    Abstract: An assembly table includes a table board, a fixing frame and a plurality of detachable table legs. The table board includes an upper surface and a lower surface, and the fixing frame is fixed on the lower surface of the table board. In addition, the fixing frame includes a plurality of connecting devices, connecting rods and connecting rod stability adjustment modules. The connection devices include a plurality of lock protrusions and a plurality of adjusting seats, and a plurality of openings are formed on the connecting rods for locking to the lock protrusions of the connection devices. The connecting rod stability adjustment modules are installed on the connecting devices, and each of the connecting rod stability adjusting modules includes an adjusting screw, pre-locked in a corresponding adjustment seat of the adjustment seats of the connecting devices to stably connect the connecting rods.
    Type: Application
    Filed: September 14, 2023
    Publication date: July 11, 2024
    Inventor: Chiu-Ting LIN
  • Publication number: 20240229508
    Abstract: A disc tumbler cylinder lock has a lock cylinder base, multiple discs, and multiple gaskets. The lock cylinder base has an accommodating space, a position limiting opening, and an accommodating opening. Each of the discs has a position limiting protrusion and a disc notch. Each of the gaskets has a ring body, a position limiting segment, and a rotation limiting segment. The position limiting segment protrudes outward from an outer annular surface of the ring body along a radial direction. The rotation limiting segment protrudes from the position limiting segment along an axial direction of the lock sleeve. The discs and the gaskets are staggeredly accommodated in the accommodating space. A side surface of the position limiting protrusion abuts a side surface of the position limiting opening. Two sides of the position limiting segment abut two opposite sides of the position limiting opening.
    Type: Application
    Filed: December 13, 2022
    Publication date: July 11, 2024
    Inventor: SHENG-TING LIN
  • Publication number: 20240237553
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.
    Type: Application
    Filed: March 21, 2024
    Publication date: July 11, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
  • Patent number: 12032224
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: July 9, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Sin-Hong Lin, Yung-Ping Yang, Wen-Yen Huang, Yu-Cheng Lin, Kun-Shih Lin, Chao-Chang Hu, Yung-Hsien Yeh, Mao-Kuo Hsu, Chih-Wei Weng, Ching-Chieh Huang, Chih-Shiang Wu, Chun-Chia Liao, Chia-Yu Chang, Hung-Ping Chen, Wei-Zhong Luo, Wen-Chang Lin, Shou-Jen Liu, Shao-Chung Chang, Chen-Hsin Huang, Meng-Ting Lin, Yen-Cheng Chen, I-Mei Huang, Yun-Fei Wang, Wei-Jhe Shen
  • Publication number: 20240224505
    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material.
    Type: Application
    Filed: December 1, 2023
    Publication date: July 4, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Ying Rui, Silvia Borsari, Prashant Raghu, Elisabeth Barr, Yen Ting Lin, Albert P. Chan, Martin Chen