Patents by Inventor Ting-An SHIH

Ting-An SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960106
    Abstract: The disclosure provides an augmented reality (AR) device, a notebook, and smart glasses. The AR device includes a laser source, a spatial light modulator (SLM), and a hologram optical element (HOE). The laser source provides a coherent laser ray. The SLM provides a diffraction pattern solely corresponding to the coherent laser ray. When the SLM receives the coherent laser ray, the diffraction pattern diffracts the coherent laser ray as a hologram in response to the coherent laser ray. The HOE provides a concave mirror effect merely in response to a wavelength of the coherent laser ray, wherein the HOE receives the hologram and magnifies the hologram as a stereoscopic virtual image.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: April 16, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Jung Chiu, Wei-Kuo Shih, Shih-Ting Huang
  • Publication number: 20240115227
    Abstract: A phantom-free calibration method for a computerized tomography scan has the steps of: scanning a plurality of homogeneous human tissues with a computerized tomography scanner and obtaining homogeneous human tissue scan information; scanning a tissue to be tested with the computerized tomography scanner and obtaining tissue to be tested scan information; calculating a spectral characteristic parameter of the computerized tomography scanner with a computing device using a model, wherein a standard tissue parameter of the homogeneous human tissues and the human tissue scan information are used in the model; and calculating a tissue parameter of the tissue to be tested with the computing device using the model, wherein the spectral characteristic parameter and the tissue to be tested scan information are inputted in the model. The phantom-free calibration method makes the tissue parameters of the tissue to be tested more accurate and the calibration process easier and more convenient.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 11, 2024
    Inventors: Yi-Wen Chen, Cheng-Ting Shih, Yu-Fen Chen
  • Publication number: 20240114698
    Abstract: A semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. The bottom electrode is over the substrate. The ferroelectric layer is over the bottom electrode. The noble metal electrode is over the ferroelectric layer. The non-noble metal electrode is over the noble metal electrode.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yu CHEN, Sheng-Hung SHIH, Fu-Chen CHANG, Kuo-Chi TU, Wen-Ting CHU, Alexander KALNITSKY
  • Publication number: 20240111210
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Patent number: 11950408
    Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin
  • Patent number: 11935816
    Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Jheng-Ting Jhong
  • Publication number: 20240074152
    Abstract: A semiconductor structure includes a first dielectric layer, a second dielectric layer on the first dielectric layer, a capacitor structure in the first dielectric layer and the second dielectric layer, a third dielectric layer on the second dielectric layer, a word line, a channel structure, and a gate dielectric. The word line is located in the third dielectric layer and extends across the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the word line and a portion of the third dielectric layer. The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is between a sidewall of the word line and the channel structure, and the second portion is between an inner sidewall of the third dielectric layer and the channel structure.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Chiang-Lin SHIH, Yu-Ting LIN
  • Publication number: 20240063175
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: WEI-ZHONG LI, YI-TING SHIH, CHIEN-CHUNG WANG, HSIH-YANG CHIU
  • Patent number: 11876072
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
  • Publication number: 20240013473
    Abstract: A method for three dimensional medical image construction having steps of inputting multiple two-dimensional images and a known three-dimensional image into a processing module and inputting a new two-dimensional image into the processing module to obtain a reconstructed three-dimensional image, wherein the processing module utilizes a neural network to build a reconstructed three-dimensional image by unfolding the two-dimensional image to produce a three-dimensional reconstruction.
    Type: Application
    Filed: June 16, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Wen Chen, Cheng-Ting Shih, Kui-Chou Huang, Hsin-Yuan Fang, Kai-Cheng Hsu
  • Patent number: 11844705
    Abstract: An implant guide system for hip replacement surgery includes an angle guide member and a first positioning plate. The angle guide member has a body and a protrusion that are substantially connected to each other. The body has a curved surface corresponding in shape to a surface of a patient's acetabulum. The protrusion has a first through hole extending to the body. An acute angle is defined between an extension line of the first through hole and a flat surface of the body. The first positioning plate has a first holding portion and a first spacing portion that are substantially connected to each other. The first spacing portion has a second through hole, a third through hole and a fourth through hole that are parallel to each other.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 19, 2023
    Assignees: UNITED ORTHOPEDIC CORPORATION, CHINA MEDICAL UNIVERSITY
    Inventors: Jiann-Jong Liau, Chih-Hao Chang, Kui-Chou Huang, Yi-Wen Chen, Cheng-Ting Shih
  • Patent number: 11786393
    Abstract: An ostomy pouching device for the removal of biological waste from a patient. An embodiment of an ostomy pouching device includes an outer container housing an inner bag for receiving waste from a patient's bowel. The device includes a bowel connector to connect the bowel to the inner bag. The outer container includes an air exit aperture through which air may exit the container as it is displaced as the inner bag expands, and a gas tunnel for removing gas from the inner bag.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 17, 2023
    Inventors: Chih-Hao Lin, Wan-Chen Shen, Wei-Ting Shih
  • Patent number: 11631827
    Abstract: An electroluminescent display panel and a manufacturing method thereof, and a display device. Each of a plurality of pixel units included in the electroluminescent display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel, respectively, each of the sub-pixels includes a first electrode, and a light-emitting layer, respectively, taking a planar surface of the first electrode facing the light-emitting layer as a reference plane, the light-emitting layer of the first sub-pixel is on a first anti-node of a first standing wave, the light-emitting layer of the second sub-pixel is on a second anti-node of a second standing wave, and the light-emitting layer of the third sub-pixel is on a second anti-node of a third standing wave.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 18, 2023
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yue Hu, Xinxin Wang, Huai Ting Shih, Chin Lung Liao
  • Publication number: 20230061312
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: WEI-ZHONG LI, YI-TING SHIH, CHIEN-CHUNG WANG, HSIH-YANG CHIU
  • Patent number: 11538920
    Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC. The conventional electric field crowding effect occurring at the trench corner is greatly solved, thus increasing breakdown voltages thereof.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 27, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu, Yi-Ting Shih
  • Patent number: 11532577
    Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
  • Publication number: 20220272075
    Abstract: A method is provided to enhance efficiency of sensor event data transmission over network. Specifically, a method is described to buffer a set of sensor data, to group one or more of the set of sensor data having a same type for batch processing. The batch processing includes compressing and securing operations on the grouped sensor data and restoring the original message sequence of the grouped sensor data.
    Type: Application
    Filed: March 15, 2022
    Publication date: August 25, 2022
    Inventors: Wei-Ting Chou, Chih-Hsiung Liu, Hao-Ting Shih, Joey H.Y. Tseng
  • Patent number: 11356420
    Abstract: A single Internet of Things (IoT) gateway flow computer (either on a gateway machine or a non-gateway machine) that controls flow through both of the following types of gateways: (i) cloud gateways; and (ii) edge gateways. Both overall configuration and sub-configuration are automatically and dynamically controlled by the single, system-wide IoT gateway flow computer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Hao-Ting Shih, Chih-Hsiung Liu, Joey H. Y. Tseng, Yi-Hong Wang
  • Publication number: 20220148923
    Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 12, 2022
    Applicant: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu, Yi-Ting Shih
  • Publication number: 20220125601
    Abstract: An implant guide system for hip replacement surgery includes an angle guide member and a first positioning plate. The angle guide member has a body and a protrusion that are substantially connected to each other. The body has a curved surface corresponding in shape to a surface of a patient's acetabulum. The protrusion has a first through hole extending to the body. An acute angle is defined between an extension line of the first through hole and a flat surface of the body. The first positioning plate has a first holding portion and a first spacing portion that are substantially connected to each other. The first spacing portion has a second through hole, a third through hole and a fourth through hole that are parallel to each other.
    Type: Application
    Filed: October 7, 2021
    Publication date: April 28, 2022
    Inventors: Jiann-Jong Liau, Chih-Hao Chang, Kui-Chou Huang, Yi-Wen Chen, Cheng-Ting Shih