Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A portable data accessing device and more particularly the use of multi-port interfaces on a data accessing device disclosed. The multi-port data accessing device includes an inner body, one or a plurality of moving-caps, one or a plurality of grips, a pump-action and one or a plurality of locking/releasing mechanisms.

Abstract: A smart speaker includes an outer casing, a speaker module, and a microphone module is provided. The outer casing includes a first housing and a second housing assembled to each other. The speaker module is disposed in the first housing. The microphone module includes a circuit board and at least one microphone. The circuit board is assembled to the second housing and separated from the first housing. The microphone is disposed on the circuit board.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for measuring and controlling local impedances at a substrate support in a plasma processing chamber during processing of a substrate. A substrate support includes a plurality of substrate support pins wherein the radio frequency voltage, current and phase of each of the plurality of substrate support pins are measured and impedances of the support pins are adjusted in real time. Each of the substrate support pins is coupled to an associated adjustable impedance circuit that may be remotely controlled. In one embodiment a variable capacitor is used to adjust the impedance of the impedance circuit coupled to the associated substrate support pin and may be remotely adjusted with a stepper motor.

Abstract: An example operation may include one or more of storing an index that comprises identifiers of role-based access privileges for a plurality of users with respect to a database, receiving a database query associated with a user from a software program, identifying data records within the database that the user has permission to access based on database accessibility rights of the user stored within the index, prior to execution of the database query, loading the identified data records into the memory and filtering out other data records from the database which the user does not have permission to access, and executing the database query on the identified data records loaded from the database and returning query results from the execution to the software program.

Abstract: A game board device is provided for carrying and identifying game pieces that are divided into different piece types. The game board device includes a board, a plurality of optically identifying modules, and a processing module electrically coupled to the optically identifying modules. The optically identifying modules respectively correspond in position to detection regions of the board. Each of the optically identifying modules includes a light emitter that can emit light toward the corresponding detection region and a light receiver that can receive light reflected by the corresponding detection region. When any one of the detection regions is in an unoccupied mode, the corresponding optically identifying module can emit an unoccupied signal. When any one of the detection regions is in an occupied mode, the corresponding optically identifying module enables an identification signal that corresponds to the piece type of the corresponding game piece to be emitted therefrom.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: A novel additive comprising an oxamide additive with long chains is described herein. The additive can be incorporated into a thermoplastic polymer to form a thermoplastic polymer composite. The additive modifies the surface of the thermoplastic polymer to render the oil, water or dust repellent properties to the thermoplastic polymer composite.

Abstract: A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface opposite the first surface. An absolute difference of the FWHM of the characteristic peaks of (111) planes of the first surface and the second surface analyzed by GIXRD is less than 0.14, the first and the second surfaces each have a nanoindentation hardness of 0.3 GPa to 3.0 GPa, and the yield strength of the electrolytic copper foil is more than 230 MPa. By controlling the absolute difference of the FWHM of the characteristic peaks of (111) plane of these two surfaces, the nanoindentation hardness of these two surfaces and the yield strength, the electrolytic copper foil can have improved tolerance to the repeated charging and discharging and reduced warpage, thereby improving the yield rate and value of the lithium-ion cell.

Abstract: Synchronously negotiating an object's creation time including identifying, by a first storage system among the two or more storage systems, a request to store a second updated version of the object; detecting, by the first storage system, a communications disruption among the two or more storage systems; and establishing, in dependence upon a local clock of the first storage system and a latest observed creation time associated with the object, a creation time for the second updated version of the object.

Abstract: A ghost key preventing circuit includes plural driving lines, plural sensing lines, plural key switches, plural bias resistors and a controller. The plural driving lines and the plural sensing lines are collaboratively formed as a matrix circuit. The plural key switches are included in the matrix circuit. The plural bias resistors are connected with the corresponding sensing lines. When the key switch of a specified switch circuit is turned on, a divided voltage is generated and outputted from the specified switch circuit. The controller judges whether the key switch of the specified switch circuit is normally turned on or the key switch is a ghost key according to the divided voltage.

Abstract: A semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. The bottom electrode is over the substrate. The ferroelectric layer is over the bottom electrode. The noble metal electrode is over the ferroelectric layer. The non-noble metal electrode is over the noble metal electrode.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. The semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. In addition, the dielectric structure includes a porous material or an air gap. The semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.

Abstract: A vinyl-containing copolymer is copolymerized from (a) first compound, (b) second compound, and (c) third compound. (a) First compound is an aromatic compound having a single vinyl group. (b) Second compound is polybutadiene or polybutadiene-styrene having side vinyl groups. (c) Third compound is an acrylate compound. The vinyl-containing copolymer includes 0.003 mol/g to 0.010 mol/g of benzene ring, 0.0005 mol/g to 0.008 mol/g of vinyl group, and 1.2*10?5 mol/g to 2.4*10?4 mol/g of ester group.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature coupled to the vertical stack of channel members and adjacent the gate structure; and a dielectric feature disposed between the source/drain feature and the substrate, in a cross-sectional view, the dielectric feature includes a V-shape sidewall surface.

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.