Patents by Inventor Ting-Chang Hsu

Ting-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250029005
    Abstract: A method includes accessing a plurality of weight matrices of a machine learning model. The method also includes, for each weight matrix, decomposing the weight matrix into a U matrix, an S matrix, and a V matrix using singular value decomposition. The S matrix is a diagonal matrix, and a singular group corresponds to each element in the S matrix. The method further includes, for each weight matrix, determining an importance score of each singular group. The importance score of the singular group represents a change in loss if the singular group is removed from the machine learning model. The method also includes, for each weight matrix, ranking the singular groups across the plurality of weight matrices based on the importance scores. In addition, the method includes, for each weight matrix, identifying one or more of the singular groups to prune based on the ranking of the singular groups.
    Type: Application
    Filed: May 20, 2024
    Publication date: January 23, 2025
    Inventors: Ting Hua, Xiao Li, Shangqian Gao, Yen-Chang Hsu, Yilin Shen, Hongxia Jin
  • Patent number: 12205819
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Ting-Hung Hsu, Jia-Ni Yu, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20250021826
    Abstract: In one embodiment, a method includes accessing at least a portion of a training dataset for a trained neural network that includes multiple layers, where each layer includes a number of parameters, and where the training dataset includes multiple training samples that each include an input and a ground-truth output used to train the trained neural network. The method further includes training a hypernetwork to generate a layer-specific compression mask for each of one or more of the multiple layers of the trained neural network. The method further includes generating, by the trained hypernetwork, a final layer-specific compression mask for the trained neural network and compressing the trained neural network by reducing, for each of the one or more layers of the neural network, the number of parameters of that layer according to the final layer-specific compression mask.
    Type: Application
    Filed: April 8, 2024
    Publication date: January 16, 2025
    Inventors: Shangqian Gao, Ting Hua, Yen-Chang Hsu, Yilin Shen, Hongxia Jin
  • Publication number: 20240385507
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 12124163
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 11860530
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20230367197
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20220350235
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 11402743
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20220066312
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 7683979
    Abstract: Each Multi-domain Vertical Alignment (MVA) pixel structures on a display panel array includes at least two sub-pixels. By adjusting the channel W/L ratios of the transistors in the sub-pixels, the sub-pixels may have different display voltages so as to improve the display quality in a slant vision. A transistor is disposed between one of the sub-pixels and a common line (Vcs) as the dispersion path for remaining electric charges to improve the condition of burn-in.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: March 23, 2010
    Assignee: Chunghwa Picture Tubes, Ltd
    Inventors: Hsien-Chun Wang, Ting-Chang Hsu
  • Publication number: 20090231505
    Abstract: Each Multi-domain Vertical Alignment (MVA) pixel structures on a display panel array includes at least two sub-pixels. By adjusting the channel W/L ratios of the transistors in the sub-pixels, the sub-pixels may have different display voltages so as to improve the display quality in a slant vision. A transistor is disposed between one of the sub-pixels and a common line (Vcs) as the dispersion path for remaining electric charges to improve the condition of burn-in.
    Type: Application
    Filed: September 5, 2008
    Publication date: September 17, 2009
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Hsien-Chun Wang, Ting-Chang Hsu
  • Publication number: 20090079669
    Abstract: A flat panel display is provided. The flat panel display includes a display panel, a gate driver, a source driver and a signal switching unit. The gate driver outputs a gate signal. The signal switching unit turns on the first terminal and the second terminal thereof to deliver the gate signal to a first scan line during a preceding half period of a frame period. Moreover, the signal switching unit turns on the first terminal and the third terminal thereof during a rear half period of the frame period, so that the gate signal, which is previously delivered to the first scan line, is delivered to the second scan line at this time. In this way, the source driver drives the display panel in coordination with the gate signal delivered by the first and second scan lines.
    Type: Application
    Filed: July 23, 2008
    Publication date: March 26, 2009
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Tzu-Chien Huang, Hsien-Chun Wang, Ting-Chang Hsu
  • Publication number: 20080239190
    Abstract: A pixel structure includes a scan line, a data line, a first thin film transistor (TFT), a second TFT, a first pixel electrode, a second pixel electrode and a third pixel electrode. The first TFT and the second TFT respectively possessing a first drain electrode and a second drain electrode are electrically connected to the scan line and the data line. The first pixel electrode is electrically connected to the first drain electrode. The second pixel electrode is placed on and coupled to parts of the first drain electrode, and the third pixel electrode is placed on and coupled to parts of the second drain electrode. As a result, the pixel structure is capable of reducing display quality variations arisen from different viewing angles.
    Type: Application
    Filed: July 26, 2007
    Publication date: October 2, 2008
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Ting-Chang Hsu, Hsien-Chun Wang, Tzu-Chien Huang