Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.

Abstract: A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line.

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract: A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line.

Abstract: A coffee maker allowing simultaneous brewing and frothing includes a steam boiler, a brewing unit, and a frothing unit. Steam from the steam boiler is respectively introduced into both the brewing unit and the frothing unit. The brewing unit contains a disk to accommodate a coffee pack. The frothing unit disposed on top of the steam boiler includes an inlet tube to introduce steam, a duct connecting to an inlet tube and an outlet, a suction tube connecting to one side of the duct close to the outlet. The suction tube has an opening located inside the frothing unit. A replaceable disk is movably inserted into a chamber of the brewing unit and is made in a size corresponding to that of a coffee pack.

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).