Patents by Inventor Ting-Chen Tseng
Ting-Chen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240387310Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 12094765Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: GrantFiled: January 17, 2022Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20240297053Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.Type: ApplicationFiled: May 6, 2024Publication date: September 5, 2024Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 12009226Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.Type: GrantFiled: August 27, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11862594Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.Type: GrantFiled: December 18, 2019Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11854927Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: GrantFiled: May 28, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230386906Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230386955Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230282558Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20230063181Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20220359446Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Publication number: 20220310467Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.Type: ApplicationFiled: May 28, 2021Publication date: September 29, 2022Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20220139774Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: ApplicationFiled: January 17, 2022Publication date: May 5, 2022Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11227795Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: GrantFiled: January 17, 2020Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20210225699Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20210193605Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao