Patents by Inventor Ting-Chen Tseng

Ting-Chen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387310
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 12094765
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20240297053
    Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.
    Type: Application
    Filed: May 6, 2024
    Publication date: September 5, 2024
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 12009226
    Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11862594
    Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11854927
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230386906
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230386955
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230282558
    Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230063181
    Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220359446
    Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20220310467
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 29, 2022
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220139774
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11227795
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210225699
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210193605
    Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao