Patents by Inventor Ting Cheng

Ting Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145561
    Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Hong-Ming LO, Chun-Chih LIN, Chyi-Tsong NI
  • Publication number: 20240130614
    Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 25, 2024
    Inventors: Shao Hung HUANG, Chao-Ting CHEN, Fong Hao KUO, Yu-Chung TUNG, Chu-Ming CHENG, Chi-Yuan KANG
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Patent number: 11964201
    Abstract: A modular pneumatic somatosensory device comprises a main body, a plurality of airbags, a plurality of inflating modules and a control module. The airbags are detachably disposed at different positions of the main body, and at least a part of the airbags have different sizes. The inflating modules are detachably disposed on the main body, and each inflating module is correspondingly connected with at least one of the airbags. The control module is detachably disposed on the main body and is electrically connected with the inflating modules. The control module controls the inflating modules to inflate the corresponding airbags according to a control signal.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Jen-Hui Chuang, June-Hao Hou, Chi-Li Cheng, Han-Ting Lin
  • Patent number: 11962949
    Abstract: A method of performing air pollution estimation is provided. The method is to be implemented using a processor of a computer device and includes: generating a spectral image based on an original color image of an environment under test using a spectral transformation matrix; supplying the spectral image as an input into an estimating model for air pollution estimation; and obtaining an estimation result from the estimating model indicating a degree of air pollution of the environment under test.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 16, 2024
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Chia-Cheng Huang, Ting-Chun Men
  • Publication number: 20240116673
    Abstract: A transport mechanism of a server rack including a carrier plate, a server rack disposed and fixed onto a top surface of the carrier plate, and multiple supporting assemblies respectively stacked onto a bottom surface of the carrier plate is provided. Each of the supporting assemblies has at least one cushion member. The cushion member has at least one hollow portion, and an opening of the hollow portion is exposed to an environment. The stiffness of the cushion member is smaller than the stiffness of the carrier plate. A pallet structure is also provided.
    Type: Application
    Filed: November 16, 2022
    Publication date: April 11, 2024
    Applicant: Wiwynn Corporation
    Inventors: Hao-Ting Cheng, Jheng-Ying Jiang, Pei-Pei Lee
  • Patent number: 11955370
    Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Publication number: 20240096885
    Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Patent number: 11934106
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Yen Liu, Hui-Fang Kuo, Chian-Ting Huang, Wei-Cyuan Lo, Yung-Feng Cheng, Chung-Yi Chiu
  • Patent number: 11928074
    Abstract: A USB active optical cable and a plug capable of managing power consumption and state. The USB active optical cable and plug respectively comprises a first plug, a second plug, and an optical transmission medium used to connect the first plug and the second plug; the first plug and the second plug are configured to operate different operating states, including an initialization mode, a transmission mode, and a power saving mode, and they can switch between the different operating states. The USB active optical cable and plug are both based on the separate control of the transmitting unit and the receiving unit to distinguish different operating modes, provide necessary operating requirements and mode switching conditions for each mode, and also enable the checking and transmission of the plugging state in the power saving mode, thus facilitate the power consumption management of the active optical cable.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: March 12, 2024
    Assignee: EVERPRO (WUHAN) TECHNOLOGIES COMPANY LIMITED
    Inventors: Ting Chen, Hui Jiang, Xinliang Zhou, Dezhen Li, Yan Li, Yufeng Cheng, Liang Xu, Jinfeng Tian
  • Publication number: 20240077726
    Abstract: A display device is configured to determine a target location. The display device includes a waveguide element, a display panel and a processor. The waveguide element is configured to receive an image and reflect the image to an eyeball location. The display panel is located at one side of the waveguide element. The display panel has a plurality of pixel units. The display panel is located between the waveguide element and the target location. The processor is electrically connected to the display panel. The processor is configured to determine the pixel units in a blocking area of the display panel to be opaque. The blocking area of the display panel overlaps the target location. The display panel displays the pixel units in the blocking area as grayscale according to the processor.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 7, 2024
    Inventors: Yeh-Wei YU, Ko-Ting CHENG, Pin-Duan HUANG, Ching-Cherng SUN
  • Publication number: 20240080270
    Abstract: A method for automatically regulating an explicit congestion notification (ECN) of a data center network based on multi-agent reinforcement learning is provided. The method specifically includes steps 1 to 3. In step 1, an ECN threshold regulation of a data center network is modelled as a multi-agent reinforcement learning problem. In step 2, an independent proximal policy optimization (IPPO) algorithm in multi-agent reinforcement learning is used for training according to features of the data center network. In step 3, offline pre-training is combined with online incremental learning such that a model deployed on each switch is capable of rapidly adapting to a dynamic data center network environment.
    Type: Application
    Filed: August 23, 2023
    Publication date: March 7, 2024
    Inventors: Ting WANG, Puyu CAI, Kai CHENG
  • Patent number: 11917955
    Abstract: Apparatus, systems and methods for irrigating lands are disclosed. In one example, an irrigation system is disclosed. The irrigation system includes a gate and a microcontroller unit (MCU). The gate is configured for adjusting a water flow for irrigating a piece of land. The MCU is configured for controlling the gate to adjust the water flow based on environmental information related to the piece of land.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Cheng Huang, Tai-Hua Yu, Shui-Ting Yang, Chao-Te Lee, Ching Rong Lu
  • Publication number: 20240069427
    Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a solvent dipping treatment is performed to the nanotube layer by applying bubbles in a solvent to the nanotube layer.
    Type: Application
    Filed: March 2, 2023
    Publication date: February 29, 2024
    Inventors: Ting-Pi SUN, Pei-Cheng HSU, Hsin-Chang LEE
  • Patent number: 11916091
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 11916130
    Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 27, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kuen-Ting Shiu, Tak H. Ning, Jeng-Bang Yau, Cheng-Wei Cheng, Ko-Tao Lee
  • Publication number: 20240064217
    Abstract: A timing control management method includes receiving a real-time protocol (RTP) packet by a jitter buffer management module, generating a playout delay range according to the RTP packet, transmitting the playout delay range to a reordering timer management module, generating a timer adjustment command from the reordering timer management module to a transport layer reordering function module, and adjusting a reordering timer according to the playout delay range by the transport layer reordering function module after the timer adjustment command is received by the transport layer reordering function module.
    Type: Application
    Filed: June 2, 2023
    Publication date: February 22, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yi-Ting Cheng, Yu-Hao Hsieh
  • Publication number: 20240021698
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsien-Wen WAN, Yi-Ting CHENG, Ming-Hwei HONG, Juei-Nai KWO, Bo-Yu YANG, Yu-Jie HONG
  • Publication number: 20240007793
    Abstract: A package structure of a micro speaker is provided. The package structure includes a substrate having a hollow chamber, a diaphragm suspended over the hollow chamber, a coil embedded in the diaphragm, a carrier board disposed on a bottom surface of the substrate, a first permanent magnetic element disposed on the carrier board and in the hollow chamber, and a lid wrapped around the substrate and the diaphragm. The diaphragm includes an etching pattern. One end of the lid exposes a portion of the top surface of the diaphragm.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: Yu-Xuan XU, Li-Jen CHEN, Yu-Ting CHENG, Shih-Chin GONG