Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a solvent dipping treatment is performed to the nanotube layer by applying bubbles in a solvent to the nanotube layer.

Abstract: A patching device and method thereof for patching a firmware function by a patch function. When a fetch address from a processor does not correspond to the firmware function, the patching device outputs an instruction of the fetch address to respond to the processor. When the fetch address corresponds to the replaced firmware function, the patching device outputs an artificial instruction to respond to the processor. The artificial instruction is one of series of machine codes corresponding to a plurality of patch intermediary instructions utilized to direct the processor to jump to the beginning address of the patch function.

Abstract: A patching device and method thereof for patching a firmware function by a patch function. When a fetch address from a processor does not correspond to the firmware function, the patching device outputs an instruction of the fetch address to respond to the processor. When the fetch address corresponds to the replaced firmware function, the patching device outputs an artificial instruction to respond to the processor. The artificial instruction is one of series of machine codes corresponding to a plurality of patch intermediary instructions utilized to direct the processor to jump to the beginning address of the patch function.

Abstract: An electronic device comprising a ROM, a reprogrammable memory, a processor, and a patching device. The ROM stores a first function starting from a first address, the reprogrammable memory stores a second function starting from a second address, the patching device couples to the ROM and the reprogrammable memory, and the processor couples to the patching device. The patching device receives directive information from the processor and determines whether the processor is going to fetch the first function, and generates and returns a branch instruction to the processor when the processor is going to fetch the first function. After receiving the branch instruction, the processor executes the branch instruction to cause an unconditional jump to the second address and subsequently fetches the second function.

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Abstract: A memory system is provided. A processor provides a data access address. A memory device includes a predetermined number of ways. The processor selectively configures a selected number less than or equal to the predetermined number of the ways as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by memory configuration information. A memory controller determines the data access address corresponding to the cacheable region or the directly addressable region, selects only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selects only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region. A configuration controller monitors the status of the ways and adjusting the memory configuration information according to the status of the ways.

Abstract: A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information stored in control registers. A cache hit detection circuit includes an address register storing the data access address, tag memories storing tag data of the data access address, a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal, and address comparators each comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match. The tag data is adjusted to a predetermined address by the data processing device, which is the highest address of memory space of the processor.

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Abstract: A memory system includes a processor providing a data access address; a set of control registers storing memory configuration information; a memory device comprising a first predetermined number of ways, the processor selectively configuring a selected number less than or equal to the first predetermined number of the ways as cache memory belonging to a cacheable region, and configuring remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information; and a memory controller determining the data access address corresponding to the cacheable region or the directly addressable region, selecting only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selecting only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region.