Abstract: A method includes moving a wafer transport device on a transport rail, wherein the wafer transport device comprises a hoist unit configured to grip a wafer container unit; stopping the wafer transport device above a load port; after stopping the wafer transport device, reading data of a rail mark located on the transport rail; aligning an orientation of the wafer transport device according to the data of the rail mark; after aligning the orientation of the wafer transport device according to the data of the rail mark, aligning the wafer transport device with respect to a top surface of the load port; after aligning the wafer transport device with respect to the top surface of the load port, lowering the hoist unit.

Abstract: A method includes moving a wafer transport device to a position above a load port; lowering a hoist unit of the wafer transport device above the load port, wherein the wafer transport device has a plurality of belts, each of the belts is connected to the hoist unit and wound around a respective belt winding drum; detecting sound waves from the belts by using at least one acoustic sensor to measure tensions of the belts; and comparing the tensions from the belts to determine an inclination of the hoist unit.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout, wherein the first layout includes a first row and a second row adjacent to the first row; (b) dividing the first layout into a plurality of regions; (c) calculating a first density of each of the plurality of regions; (d) calculating, for a first region of the plurality of regions, a first probability of altering cell versions for cells in the first region according to the first density of the first region; (e) altering cell versions of one or more cells in the first region according to a comparison between the first probability and a first threshold; and (f) rearranging the cells in the first layout to reduce cell overlap.

Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.

Abstract: The objective of the invention is to provide a method for post-routing redundant via insertion. The method is to construct a conflict graph from a post-routing design first, to find a maximal independent set (MIS) of the conflict graph, and to replace a single via with a double via for each vertex in the maximal independent set. Furthermore, since redundant vias can be classified into on-track and off-track ones and since on-track ones have better electrical properties, the invention also presents two methods to increase the amount of on-track redundant vias while a redundant via insertion solution is given.

Abstract: The objective of the invention is to provide a method for post-routing redundant via insertion. The method is to construct a conflict graph from a post-routing design first, to find a maximal independent set (MIS) of the conflict graph, and to replace a single via with a double via for each vertex in the maximal independent set. Furthermore, since redundant vias can be classified into on-track and off-track ones and since on-track ones have better electrical properties, the invention also presents two methods to increase the amount of on-track redundant vias while a redundant via insertion solution is given.

Abstract: A large number of microelectronic circuit cells that are interconnected by a set of wiring nets are optimally placed on an integrated circuit chip such that all interconnects can be routed and the total wirelength of the interconnects is minimized. Cells are first grouped into disjoint clusters by an optimization-driven clustering technique, which uses both local and global connectivity information among the cells. This technique uses Rent's rule for combining pairs of neighboring clusters, and selects among pairs of clusters having the same Rent's exponent using distance information derived from global optimization processing. Clusters are prevented from growing to an excessive size by limiting the number of cells per cluster and the maximum area per cluster to predetermined maximum values. After the clusters are generated, they are placed using an optimization-driven placement technique, preferably "Gordian".