Abstract: A multi-band network node has selectable backhaul/fronthaul configurations. Network nodes provide multi-band operation to take advantage of higher Internet speeds and to support lower latency (>2 Gbps, <4 ms latency) applications. A greater Wi-Fi device count (capacity) is supported by implementing communication over additional bands. Increased bandwidth is made available between connected nodes by selectively combining backhaul throughputs. Hardware quality-of-service (QoS) is provided by splitting traffic flows for low latency and data applications. Network coverage is extended by dynamic assignment of backhaul connections and by configuring unused backhauls as fronthauls.

Abstract: Provided is an OLED having an anode, a cathode and an organic emissive layer disposed between the anode and the cathode.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A multi-shot moulding part structure includes a first structural part, an ink decoration layer, and a second structural part. The first structural part has a first area surface, a second area surface, and a joining surface located on the second area surface. The joining surface is non-parallel to the second area surface. The ink decoration layer is spread on the first area surface and the second area surface, but not on the joining surface. The second structural part is combined with the first structural part and covers the second area surface. The second structural part touches the joining surface. By the second structural part touching the joining surface of the first structural part that is not coated with the ink decoration layer, the structural bonding strength between the first structural part and the second structural part is enhanced.

Abstract: A composition of materials including a first compound having a structure according to Formula I

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

Abstract: A method for identifying a set of optimized financing programs to provide to a merchant may include receiving historical loan application data defining historical parameters associated with corresponding historical loan applications, replacing at least a portion of the historical parameters of the historical loan application data with new parameters associated with different loan terms to define a simulated loan data set defining simulated financing programs, determining a selection probability score for each of the simulated financing programs, the selection probability score indicating a likelihood of customer selection of each respective one of the simulated financing programs, determining a cash flow rating for each of the simulated financing programs, the cash flow rating estimating cash flow over time for the each respective one of the simulated financing programs, determining a valuation score based on the selection probability score and the cash flow rating of the each respective one of the simulated

Abstract: A novel compound selected from is disclosed.

Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.

Abstract: Systems and methods for generating, distributing, and using performance mode BIOS configurations are disclosed. Each performance mode BIOS configuration can be a unique set of BIOS setting values that have been established to optimize a particular performance parameter or set of performance parameters, such as boot speed or operating system installation speed. Based on a given hardware configuration and/or set of performance parameters, one or more performance mode BIOS configurations can be packaged and transferred to a memory of a BMC in the form of one or more configuration payloads. The BIOS Setup Utility can display all configuration payloads, such as listed by the type of performance mode (e.g., “Boot Speed Performance Mode” and “OS Installation Performance Mode”), that are available in the BMC memory and allow a user to overwrite the memory containing the current BIOS configuration with a selected configuration payload.

Abstract: Provided are organic light emitting devices (OLED) comprising an anode; a cathode, and an organic layer between the anode and the cathode, the organic layer comprising a light-emitting dopant within a host material, the light-emitting dopant being an optically active Pt complex comprising a tetradentate ligand; wherein one enantiomer of the optically active Pt complex is present in an enantiomeric excess (ee) of at least 5%. Further provided are OLEDs comprising an anode, a cathode, and an organic layer between the anode and the cathode, the organic layer the organic layer comprising a light-emitting chiral dopant within a chiral host material, the light-emitting chiral dopant being an optically active complex; wherein one enantiomer of the optically active complex of the chiral dopant is present in an ee of at least 5%, and wherein one enantiomer of the chiral host material is present in an ee of at least 5%.

Abstract: Compounds containing indolocarbazole and terphenyl building blocks are disclosed in this application. These compounds are useful for application in organic electroluminescent devices.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A container for loose powder is disclosed therein that enables free flow of loose powder between a powder reservoir of the container and an application tray of the container while the container remains closed by a lid.

Abstract: The present invention relates in part to compounds containing indolocarbazole and terphenyl building blocks. These compounds are useful for application in organic electroluminescent devices wherein the combination of indolocarbazoles with terphenyl groups leads to novel compounds that demonstrate superior device performance.

Abstract: Provided are compounds of Formula Ir(LA)m(LC)n or Pt(LA)(LB), and also provided are OLED devices using those compounds.

Abstract: A multi-band network node has selectable backhaul/fronthaul configurations. Network nodes provide multi-band operation to take advantage of higher Internet speeds and to support lower latency (> 2 Gbps, < 4 ms latency) applications. A greater Wi-Fi device count (capacity) is supported by implementing communication over additional bands. Increased bandwidth is made available between connected nodes by selectively combining backhaul throughputs. Hardware quality-of-service (QoS) is provided by splitting traffic flows for low latency and data applications. Network coverage is extended by dynamic assignment of backhaul connections and by configuring unused backhauls as fronthauls.