Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.

Abstract: A broadband linear polarization antenna structure, including a reference conductive layer, a first patch antenna, a second patch antenna, and a feeding portion, is provided. The reference conductive layer includes through holes. A first short pin is connected between the reference conductive layer and the first patch antenna, and a second short pin is connected between the first patch antenna and the second patch antenna. Each feeding portion penetrates the reference conductive layer through the through hole and is coupled to the first patch antenna.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: An unlocking transmission mechanism is driven by a power transmission shaft of an electric control system to unlock an emergency exit door lock. The unlocking transmission mechanism includes a fixed base assembly, a slidable base assembly, a linear driving assembly, a transmission member and a linkage member. The transmission member is pivotally connected to the slidable base assembly, and the linkage member is pivotally connected to the transmission member. When the linear driving assembly is driven by the power transmission shaft to drive the slidable base assembly to move along a linear sliding stroke in an unlock-driving direction, the transmission member and the linkage member are sequentially driven to drive a manual-operated press bar assembly to unlock the emergency exit door lock. In addition, a multi-selective kit for the unlocking transmission mechanism is also provided.

Abstract: Methods, devices and systems that perform VC-2 decoding are disclosed. In an embodiment, a VC-2 decoder includes three parallel data paths including top-band, current-band and bottom-band data paths. The top-band data path performs variable length decoding (VLD), inverse-quantization (IQ) and inverse-DC-prediction (IDCP) processing of a top compressed data-band. The current-band data path performs VLD, IQ and IDCP processing of a current compressed data-band. The bottom-band data path performs VLD, IQ and IDCP processing of a bottom compressed data-band. Additionally, the decoder includes a three-level inverse discrete wavelet transform (IDWT) module to perform IDWT processing to synthesize decoded source pixel values in dependence on partially-decompressed top, current and bottom data-bands produced using the three parallel data paths.

Abstract: A data de-shuffler includes a buffer having a set of addressable locations for storing data and control circuitry for de-shuffling a sequence of shuffled data samples. The control circuitry stores a first data sample of the sequence of shuffled data samples at a first location in the buffer with a first address generated from an entry in a look up table and stores a second data sample at a second location in the buffer with a second address generated by incrementing from the first address by a selected incrementation value. The first and second locations in the buffer place the first and second samples in corresponding positions in an un-shuffled sequence of samples.

Abstract: The present invention relates to a safety paper table includes two first table feet, two second table feet and a table top. The first table feet each have a main plate to both sides of which two attachment flaps with half the width of the main plate and with the same locking structure created in a manner of mirror activities are connected, respectively. Besides, Long and short locking slots with openings directed downwardly are symmetrically disposed at both sides of the main plate. In addition, indentations are formed at the bottom of the main plate adjacent to the long locking slots such that locking heads are created at the outer side of the indentations. Moreover, a pair of locking members are disposed at the center of the top of the main plate. Each locking member has a mounting slot with an opening directed downwardly. Meanwhile, the locking member is connected with the main plate through side interconnection members.

Abstract: Digital video signal processor scales in spatial and temporal domains. Linear, time-varying filter provides variable-size scaling of progressive and interlace-scan formats. Temporally, frame-rate conversion is accomplished using motion compensation. Vertical line-doubling and de-interlacing is achieved with line-based motion estimation. Bilinear interpolation provides low filtering distortion; other linear and spline functions are implemented using equivalent control functionality and arithmetic datapaths.

Abstract: A digital signal processor encodes video signals per MPEG standard to achieve multi-stage, low-complexity motion estimation for interframe video coding. A dual-stage motion prediction module processes a compressed bitstream through pixel-averaging, and then applies a Sum-Of-Absolute-Difference (SOAD) function to the bitstream. A minimum motion vector signal is thereby generated over a search range initially for rough determination, then to provide a more refined estimation, the SOAD function is re-applied to the surrounding 16.times.16 blocks, preferably by full and half-pel vertical and horizontal offsets.

Abstract: An apparatus and method for combining video signals from multiple users in a continuous presence video conferencing system. Video signals are received from each of a number of different system users. The signals include input frames each having a number of different groups-of-blocks (GOBs). The GOBs correspond to hierarchically organized video data and header information. The input frame GOBs are used to form a composite output video signal suitable for transmission to each of the system users. An output frame of the composite output signal incorporates at least one of the GOBs from the input frames of each of the users and less than all of the GOBs from the input frame of at least one of the users. The resulting output video signal provides flexible continuous presence video conferencing in which video signals from multiple users may be simultaneously displayed to all users in a selected divided-screen format.

Abstract: Four QCIF video input signals generated by participants in a multiparty video conference are combined in the coded domain to produce a merged CIF video output signal. When the CIF video output signal is transmitted back to each party's video terminal, a combined 2.times.2 image is displayed. A video signal combiner (700) combines the input video signals in the coded domain by time-division multiplexing the inputs at the GOB level. In order to maintain frame synchronization between the inputs which may be arriving at different frame repetition rates, the combiner stores the inputs in buffers (706-709) and processes (710) the temporal reference (TR) numbers associated with each frame in each input before merging the GOBs from each input in accordance with the processed TR number. Specifically, the TR of each input is offset by an initial TR number associated with each input and determined at turn-on. The offset TR in each input is then mapped onto a scale of TR numbers that is common to each input.

Abstract: A sub-band coder for video signals is disclosed, which is easily realizable in VLSI due to its simple structure. The coder uses sets of two-tap finite impulse response (FIR) filters having equal-magnitude coefficients to decompose the video signal at multiple stages. In the preferred embodiment the sub-band coder has an asymmetrical structure. With the arrangement, the sub-band decomposition effects what is equivalent to a multiple block-size Hadamard transform of the video signal in which coefficients are transmitted from various block-sized transforms of larger blocks of pixel data.